TMS320DM6441_17 Datasheet, PDF (212/236 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
HEX ADDRESS RANGE
0x01C8 1004
0x01C8 1008
Table 6-88. EMAC Control Module Registers
ACRONYM
EWCTL
EWINTTCNT
Interrupt control register
Interrupt timer count
REGISTER NAME
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HEX ADDRESS RANGE
0x01C8 2000 - 0x01C8 3FFF
Table 6-89. EMAC Control Module RAM
ACRONYM
REGISTER NAME
EMAC Control Module Descriptor Memory
6.19.2 EMAC Electrical Data/Timing
Table 6-90. Timing Requirements for MRCLK (see Figure 6-65)
NO.
1 t_c(MRCLK)
Cycle time, MRCLK
2 t_w(MRCLKH) Pulse duration, MRCLK high
3 t_w(MRCLKL) Pulse duration, MRCLK low
1
2
3
1.05 V and
1.2 V
MIN MAX
40
14
14
UNIT
ns
ns
ns
MRCLK
Figure 6-65. MRCLK Timing (EMAC - Receive)
Table 6-91. Timing Requirements for MTCLK (see Figure 6-65)
NO.
1 t_c(MTCLK)
2 t_w(MTCLKH)
3 t_w(MTCLKL)
Cycle time, MTCLK
Pulse duration, MTCLK high
Pulse duration, MTCLK low
1
2
3
1.05 V and
1.2 V
MIN MAX
40
14
14
UNIT
ns
ns
ns
MTCLK
Figure 6-66. MTCLK Timing (EMAC - Transmit)
212 Peripheral and Electrical Specifications
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