TMS320DM6441_17 Datasheet, PDF (202/236 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6441
SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010
6.17.2 I2C Electrical Data/Timing
6.17.2.1 Inter-Integrated Circuits (I2C) Timing
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Table 6-81. Timing Requirements for I2C Timings⁽¹⁾ (see Figure 6-62)
1.05 V and 1.2 V
NO.
STANDARD
MODE
FAST MODE
UNIT
MIN MAX
MIN MAX
1
t_c(SCL)
Cycle time, SCL
10
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated
START condition)
4.7
2.5
µs
0.6
µs
3
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
4
0.6
µs
4
t_w(SCLL)
5
t_w(SCLH)
6
t_{su(SDAV-SCLH)}
7
t_h(SDA-SCLL)
8
t_w(SDAH)
9
t_r(SDA)
10
t_r(SCL)
11
t_f(SDA)
12
t_f(SCL)
13
t_{su(SCLH-SDAH)}
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START
conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Setup time, SCL high before SDA high (for STOP
condition)
4.7
1.3
µs
4
0.6
µs
250
100 ⁽²⁾
ns
0 ⁽³⁾
0⁽³⁾ 0.9 ⁽⁴⁾ µs
4.7
1.3
µs
1000 20 + 0.1C_b ⁽⁵⁾ 300 ns
1000 20 + 0.1C_b ⁽⁵⁾ 300 ns
300 20 + 0.1C_b ⁽⁵⁾ 300 ns
300 20 + 0.1C_b ⁽⁵⁾ 300 ns
4
0.6
µs
14
t_w(SP)
15
C_b ⁽⁵⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0 50 ns
400
400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I²C-bus™ device can be used in a standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the standard-mode I²C-bus specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
SCL
8
4
10
6
5
1
3
12
7
14
13
3
2
Stop Start
Repeated
Start
Stop
Figure 6-62. I2C Receive Timings
202 Peripheral and Electrical Specifications
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