DAC8565ICPWG4 Datasheet, PDF (32/49 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output

DAC8565
SBAS411C – JUNE 2007 – REVISED MARCH 2011
www.ti.com
Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ
Simultaneously
• 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
1
• 2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
DB15
0
DB14
1
DB13
X
DB12 DB11–DB0
X
X
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
1
DB15
0
• 3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
DB14
1
DB13
X
DB12 DB11–DB0
X
X
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
1
DB15
1
DB14
0
DB13
X
DB12 DB11–DB0
X
X
• 4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
DB23
0
DB22
0
DB21
(LD1)
1
DB20
(LD0)
0
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
1
DB15
1
DB14
0
DB13
X
DB12 DB11–DB0
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
• 1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
0
DB16
(PD0)
1
DB15
1
DB14
1
DB13
X
• 2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB12
X
DB11–DB0
X
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
0
1
DB16
(PD0)
1
DB15
1
DB14
1
DB13
X
• 3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB12
X
DB11–DB0
X
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
0
DB16
(PD0)
1
DB15
1
DB14
1
DB13
X
• 4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB12
X
DB11–DB0
X
DB23
0
DB22
0
DB21
(LD1)
0
DB20
(LD0)
1
DB19
0
DB18
DB17
(DAC Sel 1) (DAC Sel 0)
1
1
DB16
(PD0)
1
DB15
1
DB14
1
DB13
X
DB12 DB11–DB0
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
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