DAC8565ICPWG4 Datasheet, PDF (29/49 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output

DAC8565
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SYNC INTERRUPT
In a normal write sequence, the SYNC line stays low
for at least 24 falling edges of SCLK and the
addressed DAC register updates on the 24th falling
edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write
sequence; the shift register resets and the write
sequence is discarded. Neither an update of the data
buffer contents, DAC register contents, nor a change
in the operating mode occurs (as shown in
Figure 95).
POWER-ON RESET TO ZERO-SCALE OR
MIDSCALE
The DAC8565 contains a power-on reset circuit that
controls the output voltage during power-up.
Depending on the RSTSEL signal, on power-up, the
DAC registers are reset and the output voltages are
set to zero-scale (RSTSEL = 0) or midscale (RSTSEL
= 1); they remain that way until a valid write
sequence and load command are made to the
respective DAC channel. The power-on reset is
useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up.
No device pin should be brought high before power is
applied to the device. The internal reference is
powered on by default and remains that way until a
valid reference-change command is executed.
SBAS411C – JUNE 2007 – REVISED MARCH 2011
LDAC FUNCTIONALITY
The DAC8565 offer both a software and hardware
simultaneous update function. The DAC
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs.
DAC8565 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous updates,
the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. To do an LDAC
operation, single-channel store(s) should be done
(loading DAC buffers) by setting LD0 and LD1 to '0'.
Multiple single-channel updates can be done in order
to set different channel buffers to desired values and
then make a rising edge on LDAC. Data buffers of all
channels must be loaded with desired data before an
LDAC rising edge. After a low-to-high LDAC
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output
remains unchanged after the LDAC trigger.
ENABLE PIN
For normal operation, the enable pin must be driven
to a logic low. If the enable pin is driven high, the
DAC8565 stops listening to the serial port. However,
SCLK, SYNC, and D_IN must not be kept floating, but
must be at some logic level. This feature can be
useful for applications that share the same serial port.
CLK
SYNC
24th Falling Edge
24th Falling Edge
D_IN
DB23
DB0
Invalid/Interrupted Write Sequence:
Output/Mode Does Not Update on the 24th Falling Edge
DB23
DB0
Valid Write Sequence:
Output/Mode Updates on the 24th Falling Edge
Figure 95. SYNC Interrupt Facility
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