OMAP3515_15 Datasheet, PDF (30/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
mcbsp4_dr 2
I
gpt10_pwm_ 3
IO
evt
gpio_56
4
IO
safe_mode 7
P8
NA
gpmc_ncs6 0
O
sys_
1
I
ndmareq3
mcbsp4_dx 2
IO
gpt11_pwm_ 3
IO
evt
gpio_57
4
IO
safe_mode 7
N8
NA
gpmc_ncs7 0
O
gpmc_io_dir 1
O
mcbsp4_fsx 2
IO
gpt8_pwm_e 3
IO
vt
gpio_58
4
IO
safe_mode 7
T4
W2
gpmc_clk 0
O
gpio_59
4
IO
safe_mode 7
F3
W1
gpmc_nadv_ 0
O
ale
G2
V2
gpmc_noe 0
O
F4
V1
gpmc_nwe 0
O
G3
AC12
gpmc_nbe0_ 0
O
cle
gpio_60
4
IO
safe_mode 7
U3
NA
gpmc_nbe1 0
O
gpio_61
4
IO
safe_mode 7
H1
AB10
gpmc_nwp 0
O
gpio_62
4
IO
safe_mode 7
M8
AB12
gpmc_wait0 0
I
L8
AC10
gpmc_wait1 0
I
gpio_63
4
IO
safe_mode 7
K8
NA
gpmc_wait2 0
I
gpio_64
4
IO
safe_mode 7
J8
NA
gpmc_wait3 0
I
sys_
1
I
ndmareq1
gpio_65
4
IO
safe_mode 7
D28
NA
dss_pclk 0
O
gpio_66
4
IO
safe_mode 7
D26
NA
dss_hsync 0
O
gpio_67
4
IO
safe_mode 7
D27
NA
dss_vsync 0
O
gpio_68
4
IO
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
L
0
0
vdds_ mem Yes
0
0
0
vdds_ mem No
1
1
0
vdds_ mem No
1
1
0
vdds_ mem No
L
0
0
vdds_ mem Yes
L
L
7
vdds_ mem Yes
L
0
0
vdds_ mem Yes
H
H
0
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds_ mem Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
IO CELL [13]
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
NA
LVCMOS
4
NA
LVCMOS
4
NA
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
NA
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
30
TERMINAL DESCRIPTION
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