OMAP3515_15 Datasheet, PDF (136/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
OMAP Device
sys_clkreq
sys_xtalin
Oscillator
In Bypass Mode
sys_xtalout
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Clock Squarer Source
030-010
Figure 4-3. Clock Squarer Source Connection
To connect a digital clock source, the oscillator is configured in bypass mode. The sys_clkreq pin is an
OMAP3515/03 output which can be used to switch the clock source on or off.
1. Pin sys_xtalout is not used in this mode. It must be left unconnected.
2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied;
however, this affects the performance. The input source must be configured after power up to attain
the desired system requirements.
Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental
mode of operation.
Note: There is an internal pulldown resistor of 5k Ω (max.) on sys_xtalin when the oscillator is disabled.
Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode)
NAME
f
t_sX
I_DDQ
Frequency ⁽¹⁾
DESCRIPTION
Start-up time
Current consumption on VDDS when sys_xtalin = 0 and in power-
down mode
MIN
TYP
MAX
12, 13, 16.8, 19.2, 26, or 38.4
(2)
1
UNIT
MHz
ms
μA
(1) Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in
account.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in
application mode and receives a square wave. The start-up time in this case is about 100 μs.
Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock.
Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
1 / t_c(xtalin)
t_w(xtalin)
t_J(xtalin)
t_R(xtalin)
t_F(xtalin)
t_J(xtalin)
Frequency, sys_xtalin
Pulse duration, sys_xtalin low or high
Peak-to-peak jitter⁽¹⁾, sys_xtalin
Rise time, sys_xtalin
Fall time, sys_xtalin
Frequency stability, sys_xtalin
12, 13, 16.8, 19.2, 26, or 38.4
0.45 * t_c(xtalin)
–1%
0.55 * t_c(xtalin)
1%
3.6
3.6
±25
MHz
ns
ns
ns
ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
136 CLOCK SPECIFICATIONS
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