OMAP3515_15 Datasheet, PDF (1/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
OMAP3515 and OMAP3503 Applications Processors
Check for Samples: OMAP3515, OMAP3503
1 OMAP3515 and OMAP3503 Applications Processors
1.1 Features
12
• OMAP3515 and OMAP3503 Devices:
– OMAP™ 3 Architecture
– MPU Subsystem
• Up to 720-MHz ARM® Cortex™-A8 Core
• NEON™ SIMD Coprocessor
– PowerVR® SGX™ Graphics Accelerator
(OMAP3515 Device Only)
• Tile-Based Architecture Delivering up to
10 MPoly/sec
• Universal Scalable Shader Engine: Multi-
threaded Engine Incorporating Pixel and
Vertex Shader Functionality
• Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
• Fine-Grained Task Switching, Load
Balancing, and Power Management
• Programmable High-Quality Image Anti-
Aliasing
– Fully Software-Compatible with ARM9™
– Commercial and Extended Temperature
Grades
• ARM Cortex-A8 Core
– ARMv7 Architecture
• TrustZone®
• Thumb®-2
• MMU Enhancements
– In-Order, Dual-Issue, Superscalar
Microprocessor Core
– NEON Multimedia Architecture
– Over 2x Performance of ARMv6 SIMD
– Supports Both Integer and Floating-Point
SIMD
– Jazelle® RCT Execution Environment
Architecture
– Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
– Embedded Trace Macrocell (ETM) Support
for Noninvasive Debug
• ARM Cortex-A8 Memory Architecture:
– 16-KB Instruction Cache (4-Way Set-
Associative)
– 16-KB Data Cache (4-Way Set-Associative)
– 256-KB L2 Cache
• 112KB of ROM
• 64KB of Shared SRAM
• Endianess:
– ARM Instructions – Little Endian
– ARM Data – Configurable
• External Memory Interfaces:
– SDRAM Controller (SDRC)
• 16- and 32-Bit Memory Controller with
1GB of Total Address Space
• Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
• SDRAM Memory Scheduler (SMS) and
Rotation Engine
– General Purpose Memory Controller (GPMC)
• 16-Bit-Wide Multiplexed Address and
Data Bus
• Up to 8 Chip-Select Pins with 128-MB
Address Space per Chip-Select Pin
• Glueless Interface to NOR Flash, NAND
Flash (with ECC Hamming Code
Calculation), SRAM, and Pseudo-SRAM
• Flexible Asynchronous Protocol Control
for Interface to Custom Logic (FPGA,
CPLD, ASICs, and so forth)
• Nonmultiplexed Address and Data Mode
(Limited 2-KB Address Space)
• System Direct Memory Access (sDMA)
Controller (32 Logical Channels with
Configurable Priority)
• Camera Image Signal Processor (ISP)
– CCD and CMOS Imager Interface
– Memory Data Input
– BT.601 (8-Bit) and BT.656 (10-Bit) Digital
YCbCr 4:2:2 Interface
– Glueless Interface to Common Video
Decoders
– Resize Engine
• Resize Images From 1/4x to 4x
• Separate Horizontal and Vertical Control
• Display Subsystem
– Parallel Digital Output
• Up to 24-Bit RGB
1
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2
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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