DRV8303EVM Datasheet, PDF (3/29 Pages) Texas Instruments – THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

DRV8303
www.ti.com
SLOS846A – SEPTEMBER 2013 – REVISED OCTOBER 2013
PIN FUNCTIONS
PIN
I/O ⁽¹⁾
NAME
NO.
DESCRIPTION
OCTW
1
O Over current or/and over temperature warning indicator. This output is open drain with external pull-up
resistor required. Programmable output mode via SPI registers.
FAULT
2
O Fault report indicator. This output is open drain with external pull-up resistor required.
DTC
3
I Dead-time adjustment with external resistor to GND
SCS
4
I SPI chip select
SDI
5
I SPI input
SDO
6
O SPI output
SCLK
7
I SPI clock signal
DC_CAL
8
I When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
calibration can be done through external microcontroller.
GVDD
9
P Internal gate driver voltage regulator. GVDD cap should connect to GND
CP1
10
P Charge pump pin 1, ceramic cap should be used between CP1 and CP2
CP2
11
P Charge pump pin 2, ceramic cap should be used between CP1 and CP2
EN_GATE
12
I Enable gate driver and current shunt amplifiers.
INH_A
13
I PWM Input signal (high side), half-bridge A
INL_A
14
I PWM Input signal (low side), half-bridge A
INH_B
15
I PWM Input signal (high side), half-bridge B
INL_B
16
I PWM Input signal (low side), half-bridge B
INH_C
17
I PWM Input signal (high side), half-bridge C
INL_C
18
I PWM Input signal (low side), half-bridge C
DVDD
19
P Internal 3.3V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified to
drive external circuitry.
REF
20
I Reference voltage to set output of shunt amplfiiers with a bias voltage which equals to half of the
voltage set on this pin. Connect to ADC reference in microcontroller.
SO1
21
O Output of current amplifier 1
SO2
22
O Output of current amplifier 2
AVDD
23
P Internal 6V supply voltage, AVDD cap should always be installed and connected to AGND. This is an
output, but not specified to drive external circuitry.
AGND
24
P Analog ground pin
PVDD
25
P Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD cap should
connect to GND
SP2
26
I Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
SN2
27
I Input of current amplifier 2 (connecting to negative input of amplifier).
SP1
28
I Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground
side of the sense resistor for the best commom mode rejection.
SN1
29
I Input of current amplifier 1 (connecting to negative input of amplifier).
SL_C
30
I Low-Side MOSFET source connection, half-bridge C. Low-side V_DS measured between this pin and
SH_C.
GL_C
31
O Gate drive output for Low-Side MOSFET, half-bridge C
SH_C
32
I High-Side MOSFET source connection, half-bridge C. High-side V_DS measured between this pin and
PVDD.
GH_C
33
O Gate drive output for High-Side MOSFET, half-bridge C
BST_C
34
P Bootstrap cap pin for half-bridge C
SL_B
35
I Low-Side MOSFET source connection, half-bridge B. Low-side V_DS measured between this pin and
SH_B.
GL_B
36
O Gate drive output for Low-Side MOSFET, half-bridge B
SH_B
37
I High-Side MOSFET source connection, half-bridge B. High-side V_DS measured between this pin and
PVDD.
(1) KEY: I =Input, O = Output, P = Power
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