DRV8303EVM Datasheet, PDF (14/29 Pages) Texas Instruments – THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

DRV8303
SLOS846A – SEPTEMBER 2013 – REVISED OCTOBER 2013
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that (so same FET will be on again) if PWM signal is still holding high. Since all three phases or 6
FETs share a single timer, if more than one FET get OC, the FETs will not be back to normal until the
all FETs that have OC event pass 64µs.
– If PWM signal is toggled for this FET during timer running period, device will resume normal operation
for this toggled FET. So real off-time could be less than 64uS in this case.
– If two FETs get OC and one FET’s PWM signal gets toggled during timer running period, this FET will
be back to normal, and the other FET will be off till timer end (unless its PWM is also toggled)
2. OC latch shut down mode
When OC occurs, device will turn off both high side and low side FETs in the same phase if any of the FETs
in that phase has OC.
3. Report only mode
No protection action will be performance in this mode. OC detection will be reported through OCTW pin and
SPI status register. External MCU should take actions based on its own control algorithm. A pulse stretching
of 64µS will be implemented on OCTW pin so controller can have enough time to sense the OC signal.
4. OC disable mode
Device will ignore all the OC detections and will not report them either.
Under-Voltage Protection (UVP)
To protect the power output stage during startup, shutdown and other possible under-voltage conditions, the
DRV8303 provides power stage under-voltage protection by driving its outputs low whenever PVDD is below 6V
(PVDD_UV) or GVDD is below 7.5V (GVDD_UV). When UVP is triggered, the DRV8303 outputs are driven low
and the external MOSFETs will go to a high impedance state.
Over-Voltage Protection (GVDD_OV)
Device will shut down both gate driver and charge pump if GVDD voltage exceeds 16V to prevent potential issue
related to GVDD or charge pump (e.g. short of external GVDD cap or charge pump). The fault is a latched fault
and can only be reset through a transition on EN_GATE pin.
Over-Temperature Protection
A two-level over-temperature detection circuit is implemented:
• Level 1: over temperature warning (OTW)
OTW is reported through OCTW pin (over-current-temperature warning) for default setting. OCTW pin can be
set to report OTW or OCW only through SPI command. See SPI Register section.
• Level 2: over temperature (OT) latched shut down of gate driver and charge pump (OTSD_GATE)
Fault will be reported to FAULT pin. This is a latched shut down, so gate driver will not be recovered
automatically even OT condition is not present anymore. An EN_GATE reset through pin or SPI
(RESET_GATE) is required to recover gate driver to normal operation after temperature goes below a preset
value, t_{OTSD_CLR}.
SPI operation is still available and register settings will be remaining in the device during OTSD operation as long
as PVDD is still within defined operation range.
Fault and Protection Handling
The FAULT pin indicates an error event with shut down has occurred such as over-current, over-temperature,
over-voltage, or under-voltage. Note that FAULT is an open-drain signal. FAULT will go high when gate driver is
ready for PWM signal (internal EN_GATE goes high) during start up.
The OCTW pin indicates over current event and over temperature event that not necessary related to shut down.
Following is the summary of all protection features and their reporting structure:
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