DRV8303EVM Datasheet, PDF (13/29 Pages) Texas Instruments – THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

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DC_CAL
SN
DC_CAL
SP
DC_CAL
REF
DRV8303
SLOS846A – SEPTEMBER 2013 – REVISED OCTOBER 2013
400kW
S4
200kW
S3
100kW
S2
50kW
S1
5kW
_
AVDD
5kW
+
50kW
S1
100kW
S2
200kW
S3
400kW
S4
_
AVDD
100W
SO
Vref/2
50kW
+
50kW
Figure 4. Current Shunt Amplifier Simplified Block Diagram
PROTECTION FEATURES
Power Stage Protection
The DRV8303 provides over-current and under-voltage protection for the MOSFET power stage. During fault
shut down conditions, all gate driver outputs will be kept low to ensure external FETs at high impedance state.
Over-Current Protection (OCP) and Reporting
To protect the power stage from damage due to high currents, a V_DS sensing circuitry is implemented in the
DRV8303. Based on R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be
calculated which, when exceeded, triggers the OC protection feature. This voltage threshold level is
programmable through SPI command.
There are total 4 OC_MODE settings in SPI.
1. Current Limit Mode
When current limit mode is enabled, device operates current limiting instead of OC shut down during OC
event. The over-current event is reported through OCTW pin. OCTW reporting should hold low during same
PWM cycle or for a max 64µs period (internal timer) so external controller has enough time to sample the
warning signal. If in the middle of reporting, other FET(s) gets OC, then OCTW reporting will hold low and
recount another 64µS unless PWM cycles on both FETs are ended.
There are two current control settings in current limit mode (selected by one bit in SPI and default is CBC
mode).
– Setting 1 (CBC mode): during OC event, the FET that detected OC will turn off until next PWM cycle.
– Setting 2 (off-time control mode):
– During OC event, the FET that detected OC will turn off for 64us as off time and back to normal after
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