DRV8303EVM Datasheet, PDF (15/29 Pages) Texas Instruments – THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

DRV8303
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EVENT
PVDD
undervoltage
DVDD
undervoltage
GVDD
undervoltage
GVDD
overvoltage
OTW
OTSD_GATE
External FET
overload – current
limit mode
External FET
overload – Latch
mode
External FET
overload –
reporting only
mode
SLOS846A – SEPTEMBER 2013 – REVISED OCTOBER 2013
Table 1. Fault and Warning Reporting and Handling
ACTION
External FETs HiZ;
Weak pull down of all gate
driver output
External FETs HiZ;
Weak pull down of all gate
driver output; When recovering,
reset all status registers
External FETs HiZ;
Weak pull down of all gate
driver output
External FETs HiZ;
Weak pull down of all gate driver
output
Shut down the charge pump
Won’t recover and reset through
SPI reset command or
quick EN_GATE toggling
None
Gate driver latched shut down.
Weak pull down of all gate driver
output
to force external FETs HiZ
Shut down the charge pump
LATCH
REPORTING ON REPORTING ON
FAULT PIN
OCTW PIN
N
Y
N
N
Y
N
N
Y
N
Y
Y
N
N
N
Y (in default
setting)
Y
Y
Y
REPORTING IN SPI
STATUS REGISTER
Y
N
Y
Y
Y
Y
External FETs current Limiting
(only OC detected FET)
N
N
Y
Y, indicates which phase
has OC
Weak pull down of gate driver
output and PWM logic “0” of
LS and HS in the same phase.
Y
Y
Y
Y
External FETs HiZ
Reporting only
N
N
Y
Y, indicates which phase
has OC
Copyright © 2013, Texas Instruments Incorporated
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