DRV8303EVM Datasheet, PDF (10/29 Pages) Texas Instruments – THREE PHASE PRE-DRIVER WITH DUAL CURRENT SHUNT AMPLIFIERS

DRV8303
SLOS846A – SEPTEMBER 2013 – REVISED OCTOBER 2013
CURRENT SHUNT AMPLIFIER CHARACTERISTICS
T_C = 25°C unless otherwise specified
PARAMETER
TEST CONDITIONS
G1
Gain option 1
Tc = -40°C-125°C
G2
Gain option 2
Tc = -40°C-125°C
G3
Gain Option 3
Tc = -40°C-125°C
G4
Gain Option 4
Tc = -40°C-125°C
Tc = 0-60°C, G = 10, Vstep = 2 V
Tsettling Settling time to 1%
Tc = 0-60°C, G = 20, Vstep = 2 V
Tc = 0-60°C, G = 40, Vstep = 2 V
Tc = 0-60°C, G = 80, Vstep = 2 V
Vswing
Output swing linear range
Slew Rate
G = 10
DC_offset Offset error RTI
G = 10 with input shorted
Drift_offset Offset drift RTI
Ibias
Input bias current
Vin_com Common input mode range
Vin_dif
Differential input range
Vo_bias
Output bias
With zero input current, Vref up to 6 V
CMRR_OV
Overall CMRR with gain resistor
mismatch
CMRR at DC, gain = 10
SPI CHARACTERISTICS (Slave Mode Only)
PARAMETER
TEST CONDITIONS
t_{SPI_READY}
SPI ready after EN_GATE transitions to
HIGH
PVDD > 6 V
t_CLK
t_CLKH
t_CLKL
t_{SU_SDI}
t_{HD_SDI}
t_{D_SDO}
Minimum SPI clock period
Clock high time
Clock low time
SDI input data setup time
SDI input data hold time
SDO output data delay time, CLK high to
SDO valid
C_L = 20 pF
t_{HD_SDO}
t_{SU_SCS}
t_{HD_SCS}
t_{HI_SCS}
SDO output data hold time
SCS setup time
SCS hold time
SCS minimum high time before SCS active
low
t_ACC
SCS access time, SCS low to SDO out of
high impedance
t_DIS
SCS disable time, SCS high to SDO high
impedance
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MIN
TYP
9.5
10
18
20
38
40
75
80
300
600
1.2
2.4
0.3
10
10
–0.15
–0.3
–0.5%
0.5×Vref
MAX
10.5
21
42
85
5.7
4
100
0.15
0.3
0.5%
UNIT
V/V
V/V
V/V
V/V
ns
ns
µs
µs
V
V/µs
mV
µV/C
µA
V
V
V
70
85
dB
MIN TYP MAX UNIT
5
10 ms
100
ns
40
40
20
ns
30
ns
20 ns
40
50
ns
50
ns
40
ns
10
ns
10
ns
10
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