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| OMAP3503-HIREL Datasheet, PDF (298/329 Pages) Texas Instruments – OMAP3503-HiRel Applications Processor | |||
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OMAP3503-HiRel
SPRS663 â FEBRUARY 2010
www.ti.com
Table 6-109. Correspondence Standard vs. TI Timing References (continued)
TI-OMAP
STANDARD-I2C
S/F Mode
HS Mode
I6
th(SCLH-SDAH)
THD;STA
I7
th(SCLH-RSTART)
TSU;STO
I8
tw(SDAH)
TBUF
THD;STA
TSU;STO
6.6.6 HDQ / 1-Wire Interfaces
This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single
wire to communicate between the master and the slave. The protocols employ an asynchronous return to
1 mechanism where, after any command, the line is pulled high.
6.6.6.1 HDQ Protocol
Table 6-110 and Table 6-111 assume testing over the recommended operating conditions (see
Figure 6-55 through Figure 6-58).
Table 6-110. HDQ Timing Requirements
PARAMETER
DESCRIPTION
MIN
tCYCD
Bit window
253
tHW1
Reads 1
tHW0
Reads 0
180
tRSPS
Command to host respond time(1)
(1) Defined by software.
MAX
68
UNIT
ms
PARAMETER
tB
tBR
tCYCH
tDW1
tDW0
Table 6-111. HDQ Switching Characteristics
DESCRIPTION
Break timing
Break recovery
Bit window
Sends1 (write)
Sends0 (write)
MIN
TYP
193
63
253
1.3
101
MAX
UNIT
ms
tB
tBR
HDQ
030-095
Figure 6-55. HDQ Break (Reset) Timing
HDQ
tHW 1
tHW 0
tCYCH
Figure 6-56. HDQ Read Bit Timing (Data)
030-096
298 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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Copyright © 2010, Texas Instruments Incorporated
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