OMAP3503-HIREL Datasheet, PDF (215/329 Pages) Texas Instruments – OMAP3503-HiRel Applications Processor

OMAP3503-HiRel
www.ti.com
SPRS663 – FEBRUARY 2010
5 VIDEO DAC SPECIFICATIONS
A dual-display interface equips the OMAP3503 processor. This display subsystem provides the necessary
control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one
per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the
video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1
illustrates the OMAP3503 DAC architecture. For more information, see the DSS chapter of the
OMAP3503x Technical Reference Manual (TRM) [literature number SPRUF98 ].
OMAP Device
TV DCT
tv_vfb1
DIN1[9:0]
Video DAC 1
TVOUT
BUFFER
DSS
DIN2[9:0]
Video DAC 2
tv_out1
tv_vfb2
TTVVOUUTT
B^BU^UF^FF^FEE^RR
tv_out2
vdda_dac vssa_dac
tv_vref
V_ref
CBG
Figure 5-1. Video DAC Architecture
030-018
The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and
noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and
Table 5-4.
5.1 Interface Description
Table 5-1 summarizes the external pins of the video DAC.
PIN NAME
tv_out1
Table 5-1. External Pins of 10-bit Video DAC
I/O DESCRIPTION
O TV analog output composite
DAC1 video output. An external resistor is connected between this
node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally,
note that this is the output node that drives the load (75 Ω).
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VIDEO DAC SPECIFICATIONS 215