OMAP3503-HIREL Datasheet, PDF (1/329 Pages) Texas Instruments – OMAP3503-HiRel Applications Processor

OMAP3503-HiRel
www.ti.com
OMAP3503-HiRel Applications Processor
Check for Samples: OMAP3503-HiRel
SPRS663 – FEBRUARY 2010
1 OMAP3503-HiRel Applications Processor
1.1 Features
123
• OMAP3503 Applications Processor:
– OMAP™ 3 Architecture
– MPU Subsystem
• Up to 720-MHz ARM Cortex™-A8 Core
• NEON™ SIMD Coprocessor
– Fully Software-Compatible With ARM9™
– Commercial and Extended Temperature
Grades
• ARM Cortex™-A8 Core
– ARMv7 Architecture
• Trust Zone®
• Thumb®-2
• MMU Enhancements
– In-Order, Dual-Issue, Superscalar
Microprocessor Core
– NEON™ Multimedia Architecture
– Over 2x Performance of ARMv6 SIMD
– Supports Both Integer and Floating Point
SIMD
– Jazelle® RCT Execution Environment
Architecture
– Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
– Embedded Trace Macrocell (ETM) Support
for Non-Invasive Debug
• ARM Cortex™-A8 Memory Architecture:
– K-Byte Instruction Cache (4-Way
Set-Associative)
– K-Byte Data Cache (4-Way Set-Associative)
– K-Byte L2 Cache
• 112K-Byte ROM
• 64K-Byte Shared SRAM
• Endianess:
– ARM Instructions - Little Endian
– ARM Data – Configurable
• External Memory Interfaces:
– SDRAM Controller (SDRC)
• 16, 32-bit Memory Controller With
1G-Byte Total Address Space
• Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
• SDRAM Memory Scheduler (SMS) and
Rotation Engine
– SDRAM Controller (SDRC)
• 16, 32-bit Memory Controller With
1G-Byte Total Address Space
• Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
• SDRAM Memory Scheduler (SMS) and
Rotation Engine
– General Purpose Memory Controller (GPMC)
• 16-bit Wide Multiplexed Address/Data Bus
• Up to 8 Chip Select Pins With 128M-Byte
Address Space per Chip Select Pin
• Glueless Interface to NOR Flash, NAND
Flash (With ECC Hamming Code
Calculation), SRAM and Pseudo-SRAM
• Flexible Asynchronous Protocol Control
for Interface to Custom Logic (FPGA,
CPLD, ASICs, etc.)
• Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
• System Direct Memory Access (sDMA)
Controller (32 Logical Channels With
Configurable Priority)
• Camera Image Signal Processing (ISP)
– CCD and CMOS Imager Interface
– Memory Data Input
– RAW Data Interface
– BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit)
Interface
– A-Law Compression and Decompression
– Preview Engine for Real-Time Image
Processing
– Glueless Interface to Common Video
Decoders
– Histogram Module/Auto-Exposure,
Auto-White Balance, and Auto-Focus Engine
– Resize Engine
• Resize Images From 1/4x to 4x
• Separate Horizontal/Vertical Control
• Display Subsystem
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated