OMAP-L138_11 Datasheet, PDF (279/287 Pages) Texas Instruments – OMAP-L138 C6-Integra DSP+ARM Processor

OMAP-L138
www.ti.com
SPRS586C – JUNE 2009 – REVISED MAY 2011
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
Figure 6-1 provides a legend for reading the complete device.
X OMAPL138
( ) ZWT ( ) 3
PREFIX
X = Experimental Device
P = Prototype Device
Blank = Production Device
DEVICE
OMAPL138
SILICON REVISION^(C)
Blank = Silicon Revision 1.0
A = Silicon Revision 1.1
B = Silicon Revision 2.0 or 2.1
DEVICE SPEED RANGE ^(B)
3 = 300 MHz (Revision 1.x)
3 = 375 MHz (Revision 2.x)
4 = 456 MHz (Revision 2.x)
TEMPERATURE RANGE (JUNCTION)
Blank = 0°C to 90°C (Commercial Grade)
D = -40°C to 90°C (Industrial Grade)
A = -40°C to 105°C (Extended Grade)
PACKAGE TYPE ^(A)
ZCE = 361 Pin Plastic BGA, with Pb-free
Soldered Balls [Green], 0.65 mm Ball Pitch
ZWT = 361 Pin Plastic BGA, with Pb-free
Soldered Balls [Green], 0.8 mm Ball Pitch
A. BGA = Ball Grid Array
B. The device speed range symbolization indicates the maximum CPU frequency when the core voltage CV_DD is set to
1.2 V.
C. Parts marked revision B are silicon revision 2.1 if '2.1' is marked on the package, and silicon revision 2.0 if there is no
'2.1' marking.
Figure 6-1. Device Nomenclature
6.2 Documentation Support
The following documents are available on the Internet at www.ti.com. Tip: Enter the literature number in
the search box.
DSP Reference Guides
SPRUG82
TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
SPRUFE8
TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
SPRUFK5
TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides
an overview and briefly describes the peripherals available on the device.
SPRUGM7 OMAP-L138 Applications Processor System Reference Guide . Describes the
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