OMAP-L138_11 Datasheet, PDF (160/287 Pages) Texas Instruments – OMAP-L138 C6-Integra DSP+ARM Processor

OMAP-L138
SPRS586C – JUNE 2009 – REVISED MAY 2011
www.ti.com
5.16 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
• Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it
more tolerant to DMA latency
If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 1 or greater.
5.16.1 McBSP Peripheral Register Description(s)
McBSP0
BYTE ADDRESS
0x01D1 0000
0x01D1 0004
0x01D1 0008
0x01D1 000C
0x01D1 0010
0x01D1 0014
0x01D1 0018
0x01D1 001C
0x01D1 0020
0x01D1 0024
0x01D1 0028
0x01D1 002C
0x01D1 0030
0x01D1 0034
0x01D1 0038
0x01D1 003C
0x01D1 0800
0x01D1 0810
0x01D1 0814
0x01D1 0818
0x01D1 081C
0x01F1 0000
0x01F1 0000
McBSP1
BYTE ADDRESS
0x01D1 1000
0x01D1 1004
0x01D1 1008
0x01D1 100C
0x01D1 1010
0x01D1 1014
0x01D1 1018
0x01D1 101C
0x01D1 1020
0x01D1 1024
0x01D1 1028
0x01D1 102C
0x01D1 1030
0x01D1 1034
0x01D1 1038
0x01D1 103C
0x01D1 1800
0x01D1 1810
0x01D1 1814
0x01D1 1818
0x01D1 181C
0x01F1 1000
0x01F1 1000
Table 5-58. McBSP/FIFO Registers
ACRONYM
REGISTER DESCRIPTION
McBSP Registers
DRR
McBSP Data Receive Register (read-only)
DXR
McBSP Data Transmit Register
SPCR
McBSP Serial Port Control Register
RCR
McBSP Receive Control Register
XCR
McBSP Transmit Control Register
SRGR
McBSP Sample Rate Generator register
MCR
McBSP Multichannel Control Register
RCERE0
McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
XCERE0
McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
PCR
McBSP Pin Control Register
RCERE1
McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
XCERE1
McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
RCERE2
McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
XCERE2
McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
RCERE3
McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
XCERE3
McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
McBSP FIFO Control and Status Registers
BFIFOREV
BFIFO Revision Identification Register
WFIFOCTL
Write FIFO Control Register
WFIFOSTS
Write FIFO Status Register
RFIFOCTL
Read FIFO Control Register
RFIFOSTS
Read FIFO Status Register
McBSP FIFO Data Registers
RBUF
McBSP FIFO Receive Buffer
XBUF
McBSP FIFO Transmit Buffer
160 Peripheral Information and Electrical Specifications
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