OMAP-L138_11 Datasheet, PDF (181/287 Pages) Texas Instruments – OMAP-L138 C6-Integra DSP+ARM Processor

OMAP-L138
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SPRS586C – JUNE 2009 – REVISED MAY 2011
Table 5-80. Additional⁽¹⁾ SPI1 Master Timings, 4-Pin Enable Option⁽²⁾⁽³⁾
NO.
17 t_{d(EN A_SPC)M}
18 t_{d(SPC_ENA)M}
PARAMETER
Delay from slave
assertion of
SPI1_ENA active to
first SPI1_CLK from
master. ⁽⁴⁾
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Max delay for slave to
deassert SPI1_ENA ^{Polarity = 0, Phase = 1,}
after final SPI1_CLK ^{from SPI1_CLK falling}
edge to ensure
Polarity = 1, Phase = 0,
master does not begin
the next transfer.⁽⁵⁾
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
1.3V, 1.2V
MIN MAX
3P+5
1.1V
MIN MAX
3P+5
1.0V
MIN MAX
3P+6
UNIT
0.5M+3P+5
3P+5
0.5M+3P+5
3P+5
0.5M+3P+6
ns
3P+6
0.5M+3P+5
0.5M+3P+5
0.5M+3P+6
0.5M+P+5
0.5M+P+5
0.5M+P+6
P+5
0.5M+P+5
P+5
0.5M+P+5
P+6
ns
0.5M+P+6
P+5
P+5
P+6
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-78).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 5-81. Additional⁽¹⁾ SPI1 Master Timings, 4-Pin Chip Select Option^{(2) (3)}
NO.
19 t_{d(SCS_SPC)M}
20 t_{d(SPC_SCS)M}
PARAMETER
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Delay from
SPI1_SCS active
to first
SPI1_CLK^{(4) (5)}
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Delay from final
SPI1_CLK edge to
master
deasserting
SPI1_SCS ^{(6) (7)}
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
1.3V, 1.2V
MIN
MAX
2P-1
0.5M+2P-1
2P-1
0.5M+2P-1
0.5M+P-1
P-1
0.5M+P-1
P-1
1.1V
MIN
MAX
2P-5
1.0V
MIN
MAX
2P-6
0.5M+2P-5
0.5M+2P-6
2P-5
2P-6
0.5M+2P-5
0.5M+2P-6
0.5M+P-5
0.5M+P-6
P-5
P-6
0.5M+P-5
0.5M+P-6
P-5
P-6
UNIT
ns
ns
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-78).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Peripheral Information and Electrical Specifications 181
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