TLC5929 Datasheet, PDF (27/36 Pages) Texas Instruments – 16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control, Power-Save Mode

TLC5929
www.ti.com
SBVS159 – APRIL 2011
OUTPUT LEAKAGE DETECTION (OLD)
When IDM mode is enabled, OLD is always disabled.
Output leakage detection (OLD) detects a fault caused by a short with high resistance from OUTn to GND by
comparing the OUTn voltage to the LSD detection threshold voltage when the output on/off data are set to the off
state. OLD can also detect a short between adjacent pins. A very small current is sourced from the turned-off
OUTn to detect leaking when the SIDLD bits are '11' and BLANK is low. OLD operation is disabled when the
SIDLD bits are set to any value except '11', and then the current source is stopped. If the OUTn voltage is lower
than the programmed LSD threshold voltage, the corresponding OLD bit is set to '1' to indicate a leaking LED.
Otherwise, the OLD bit is set to '0'. The OLD result is valid for disabled outputs only. The OLD data are latched
into the SID holder when BLANK goes high. The OLD bits of the enabled outputs are always '0'. When the
device resumes operation from power-save mode, OLD cannot be executed until after the propagation delay (t_D4)
has elapsed because OLD does not work during power-save mode.
STATUS INFORMATION DATA (SID)
The status information data (SID) contains the status of the LED open detection (LOD), LED short detection
(LSD), output leakage detection (OLD), pre-thermal warning (PTW), thermal error flag (TEF), and IREF short flag
(ISF), depending on the SIDLD bits in the control data latch. When the MSB of the common shift register is set to
'0', the selected SID overwrite the lower 16 bits in the common shift register at the rising edge of LAT after the
data in the common shift register are copied to the output on/off data latch. If the MSB of the common shift
register is '1', the data in the common shift register do not change.
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without
changing the on/off control data, reprogram the common shift register with the same data currently programmed
into the on/off data latch. When LAT goes high, the output on/off data do not change, but new SID data are
loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, and ISF are shifted out of SOUT with each
rising edge of SCLK.
The SID reading must be delayed for a duration of t_D4 or more after the device resumes operation from the
power-save mode because SID does not indicate correct data during the power-save mode. The SID load
configuration and SID read timing are shown in Figure 29 and Figure 30, respectively.
Selected SID (16 bits) by SIDLD Data in the Control Data Latch
MSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT15 OUT14 OUT13 OUT12 OUT11
15
14
13
12
11
LSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT4 OUT3 OUT2 OUT1 OUT0
4
3
2
1
0
No data are loaded
into the MSB of the
common shift register
SOUT
MSB = ‘0’
Latch Common Common Common Common Common
Select Data Bit Data Bit Data Bit Data Bit Data Bit
Bit
15
14
13
12
11
16
15
14
13
12
11
LSB
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
4
3
2
1
0
4
3
2
1
0
Common Shift Register (17 Bits)
Figure 29. SID Load Configuration
SID are loaded to the
common shift register
at the rising edge of
LAT when the common
shift register MSB is ‘0’.
SIN
SLCK
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