TLC5929 Datasheet, PDF (24/36 Pages) Texas Instruments – 16-Channel, Constant-Current LED Driver with 7-Bit Global Brightness Control, Power-Save Mode

TLC5929
SBVS159 – APRIL 2011
www.ti.com
POWER-SAVE MODE
In power-save mode, the TLC5929 input current becomes 10 µA (typ). When the PSMODE bit in the control data
latch is '1', power-save mode is enabled. If the rising edge of LAT writes '0' into all bits of the output on/off data
latch or any data into the control data latch with all bits of the on/off data latch being '0', the TLC5929 goes into
power-save mode. The device stays in power-save mode until the next rising edge on SCLK is received. The
power-save mode timing is shown in Figure 25.
SIN ^Low
SCLK
LAT
1 2 34 5
14 15 16 17
12 3
BLANK
Don’t Care
PSMODE bit ^{‘1’}
in Control Data
Latch (Internal)
Output On/Off
Control Data
Latch (Internal)
OUT0
OUT1
OFF
ON
OFF
ON
Previous On/Off Data
All Data are ‘0’
OFF
OFF
OUT15
OFF
ON
OFF
Power-Save _{See (1)}
Mode
Normal mode
Normal mode
Power-Save mode⁽²⁾ (I_CC = 10 mA,typ) Normal Mode
(1) Contents depend on output on/off data.
(2) When PSMODE bit is '0', the device does not go into power-save mode even if the output on/off data is all '0'.
(3) Because it takes 20 µs (max) to return to normal mode, the first SCLK rising edge should be input at least 20 µs before OUTn is enabled.
Figure 25. Power-Save Mode Timing
LED OPEN DETECTION (LOD)
LOD detects a fault caused by an open circuit in the nth LED string, or a short from OUTn to ground, by
comparing the OUTn voltage to the LOD detection threshold voltage level (V_LOD = 0.3 V, typ). If the OUTn
voltage is lower than V_LOD, that output LOD bit is set to '1' to indicate an open LED string. Otherwise, the LOD bit
is set to '0'. LOD data are only valid for outputs that are programmed to be enabled. LOD data for outputs that
are programmed to be disabled are always '0' (see Table 11), except when IDM is enabled.
The LOD data are stored in a 16-bit register called SID holder (see the Functional Block Diagram) at the rising
edge of BLANK when the SIDLD bits are set to '01' (see Table 6). However, when the IDM is enabled, the LOD
bits are stored in the SID holder at the end of the IDM working time selected by IDMTIM (see Table 9).
The stored LOD data can be read out through the common shift register as SID at the SOUT pin. LOD/LSD data
are not valid for 0.5 µs after the output is turned on.
When the device resumes operation from power-save mode, the LOD cannot be executed before the
propagation delay (t_D4) has elapsed because LOD does not work during power-save mode.
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