BQ24153A_14 Datasheet, PDF (27/46 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

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bq24153A, bq24156A
bq24158, bq24159
SLUSAB0C – OCTOBER 2010 – REVISED JULY 2013
S SLAVE ADDRESS
R/W
‘0’ (Write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
From master to IC
From IC to master
A = Acknowledge (SDA LOW)
A = Not acknowledge (SDA
HIGH)
S = START condition
Sr = Repeated START condition
P = STOP condition
(a) F/S-Mode
F/S-Mode
HS-Mode
F/S-Mode
S HS-MASTER CODE
A ^{Sr SLAVE ADDRESS R/W}
‘0’ (write)
A REGISTER ADDRESS A DATA
Data Transferred
(n Bytes + Acknowledge)
A/A ^P
HS-Mode
Continues
(b) HS- Mode
Figure 35. Data Transfer Format in F/S Mode and H/S Mode
Sr Slave A.
Slave Address Byte
MSB
LSB
X
1
1
0
1
0
1
1
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
LSB
0
0
0
0
0
D2
D1
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the IC, which
contains the address of the register to be accessed. The IC contains five 8-bit registers accessible via a
bidirectional I²C-bus interface. Among them, four internal registers have read and write access; and one has only
read access.
REGISTER DESCRIPTION
BIT
B7 (MSB)
B6
B5
B4
Table 3. Status/Control Register (Read/Write)
Memory Location: 00, Reset State: x1xx 0xxx
NAME
TMR_RST/OTG
EN_STAT
STAT2
STAT1
READ/WRITE
Read/Write
Read/Write
Read Only
Read Only
FUNCTION
Write: TMR_RST function, write "1" to reset the safety timer (auto clear)
Read: OTG pin status, (for bq24153A/8 only) 0-OTG pin at Low level, 1-OTG pin at High
level
SLRST pin status (for bq2156A/9 only), 0-SLRST pin at LOW level, 1-SLRST pin at HIGH
level.
0-Disable STAT pin function, 1-Enable STAT pin function (default 1)
00-Ready, 01-Charge in progress, 10-Charge done, 11-Fault
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