BQ24153A_14 Datasheet, PDF (22/46 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support

bq24153A, bq24156A
bq24158, bq24159
SLUSAB0C – OCTOBER 2010 – REVISED JULY 2013
Table 1. STAT Pin Summary
CHARGE STATE
Charge in progress and EN_STAT=1
Other normal conditions
Charge mode faults: Timer fault, sleep mode, VBUS or battery overvoltage, poor input source,
VBUS UVLO, no battery, thermal shutdown
Boost mode faults (bq24153A/8 only): Timer fault, over load, VBUS or battery overvoltage, low
battery voltage, thermal shutdown
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STAT
Low
Open-drain
128-μs pulse, then open-drain
128-μs pulse, then open-drain
Control Bits in Charge Mode
CE Bit (Charge Mode)
The CE bit in the control register is used to disable or enable the charge process. A low logic level (0) on this bit
enables the charge and a high logic level (1) disables the charge.
RESET Bit
The RESET bit in the control register is used to reset all the charge parameters. Writing ‘1” to the RESET bit will
reset all the charge parameters to default values except the safety limit register, and RESET bit is automatically
cleared to zero once the charge parameters get reset. It is designed for charge parameter reset before charge
starts and it is not recommended to set the RESET bit while charging or boosting are in progress.
OPA_Mode Bit
OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the IC operates as a charger if
HZ_MODE is set to "0", refer to Table 2 for detail. When OPA_MODE=1 and HZ_MODE=0, the IC operates in
boost mode.
OPA_MODE
0
1(bq24153A/8 only)
X
Table 2. Operation Mode Summary
HZ_MODE
0
0
1
OPERATION MODE
Charge (no fault)
Charge configure (fault, V_bus > UVLO)
High impedance (V_bus < UVLO)
Boost (no faults)
Any fault go to charge configure mode
High impedance
CONTROL PINS IN CHARGE MODE
CD Pin (Charge Disable)
The CD pin is used to disable the charging process. When the CD pin is low, charge is enabled. When the CD
pin is high, charge is disabled and the charger enters high impedance (Hi-Z) mode.
SLRST Pin (Safety Limit Register 06H Reset, bq24156A/9 only)
The safety limit registers provide a means to limit both the maximum charge current and maximum battery
regulation voltage at POR regardless of subsequent attempts to increase them via I²C. When the SLRST pin is
low, bq24156A/9 will reset all the safety limits to default values, regardless of the write actions to safety limits
registers (06H). When the SLRST pin is high, the bq24156A/9 can program the safety limit register until any write
action to other registers locks the programmed safety limits.
BOOST MODE OPERATION (bq24153A/8 only)
In 32 second mode, when OTG pin is high (and OTG_EN bit is high thereby enabling OTG functionality) or the
operation mode bit (OPA_MODE) is set to 1, bq24153A/8 operates in boost mode and delivers the power to
VBUS from the battery. In normal boost mode, bq24153A/8 converts the battery voltage to V_BUS-B (about 5.05V)
and delivers a current as much as I_BO (about 200mA) to support other USB OTG devices connected to the USB
connector.
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