LM3463_12 Datasheet, PDF (26/40 Pages) Texas Instruments – LM3463 Dynamic Headroom Controller with Thermal Control Interface and Individual Channel Dimming Control

LM3463
SNVS807 – MAY 2012
www.ti.com
Group B
Group C
Group D
CH2 and CH3, controlled by the second byte
CH4, controlled by the third byte
controlled by the forth byte
A data bit is latched into the LM3463 by applying a rising edge to the DIM02 pin. After clocking 32 bits (4 data
bytes) into the LM3463, a falling edge should be applied to the DIM4 pin to indicate an EOF and load data bytes
from data buffer to output channels accordingly. Figure 14 shows the serial input waveforms to the LM3463 to
facilitate in serial interface mode. Figure 15 shows the timing parameters of the serial data interface. The PWM
dimming duty in the serial interface mode is governed by the following equation:
(12)
The PWM dimming duty at decimal data codes 01 (001h) and 02 (002h) are rounded up to 2/256. Thus the
minimum dimming duty in the serial interface mode is 2/256 or 0.781%. Figure 16 shows the relationship of the
PWM dimming duty and the code value of a data byte in the serial interface mode. The PWM dimming frequency
in serial interface mode is defined by the system clock of the LM3463. The dimming frequency in the serial
interface mode is equal to the system clock frequency divided by 256 which follows the equation below:
(13)
In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel
(1/(f_SERIAL-DIM*256)) should be no shorter than 8us, thus a dimming frequency of 488Hz is suggested to use.
DIM23
(Clock signal)
DIM01
(Data)
BIT0
LSB
BIT1
BIT2
BIT3 BIT4
One data byte
BIT5
BIT6
BIT7
MSB
DIM23
(Clock signal)
DIM01
(Data)
BYTE1
(Group D)
BYTE2
(Group C)
BYTE3
(Group B)
BYTE4
(Group A)
DIM4
(End of Frame)
BOF
One data frame
EOF
Figure 14. Input waveform to the LM3463 in serial interface mode
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