LM3463_12 Datasheet, PDF (18/40 Pages) Texas Instruments – LM3463 Dynamic Headroom Controller with Thermal Control Interface and Individual Channel Dimming Control

LM3463
SNVS807 – MAY 2012
www.ti.com
Dynamic Headroom Control (DHC)
The Dynamic Headroom Control (DHC) is a control method which aimed at minimizing the voltage drops on the
linear regulators to optimize system efficiency. The DHC circuit inside the LM3463 controls the output voltage of
the primary power supply (V_RAIL) until the voltage at any drain voltage sensing pin (V_DRn) equals 1V. The LM3463
interacts with the primary power supply through the OutP pin in a slow manner which determined by the
capacitor, C_DHC. Generally, the value of the C_DHC defines the frequency response of the LM3463. The higher the
capacitance of the C_DHC, the lower the frequency response of the DHC loop, and vice versa. Since the V_RAIL is
controlled by the LM3463 via the DHC loop, the response of the LM3463 driver stage must be set one decade
lower than the generic response of the primary power supply to secure stable operation.
The cut-off frequency of the DHC loop is governed by the following equation:
(6)
Practically, the frequency response of the primary power supply might not be easily identified (e.g. off-the-shelf
AC/DC power supply). For the situations that the primary power supply has an unknown frequency response, it is
suggested to use a 2.2uF 10V X7R capacitor for CDHC as an initial value and decrease the value of the C_DHC to
increase the response of the whole system as needed.
Holding V_RAIL In Analog Dimming Control
Due to the V-I characteristic of the LED, the forward voltage of the LED strings decreases when the forward
current is decreased. In order to compensate the rising of the voltage drop on the linear regulators when
performing analog dimming control (due to the reduction of LED forward voltages), the DHC circuit in the LM3463
reduces the rail voltage (V_RAIL) to maintain minimum voltage headroom (i.e. minimum V_DRn).
In order to ensure good response of analog dimming control, the V_RAIL is maintained at a constant level to
provide sufficient voltage headroom when the output currents are adjusted to a very low level. When the voltage
at the IOUTADJ pin is decreased from certain level to below 0.63V, the DHC circuit stops to react to the
changing of V_DRn and maintains the V_RAIL at the level while V_IOUTADJ equals 0.63V. DHC resumes when the
V_IOUTADJ is increased to above 0.63V. Figure 6 shows the relationship of the V_RAIL, V_SEn and V_IOUTADJ.
18
Submit Documentation Feedback
Product Folder Links: LM3463
Copyright © 2012, Texas Instruments Incorporated