LM3463_12 Datasheet, PDF (25/40 Pages) Texas Instruments – LM3463 Dynamic Headroom Controller with Thermal Control Interface and Individual Channel Dimming Control

LM3463
www.ti.com
SNVS807 – MAY 2012
The DIM01, DIM23, DIM4 and DIM5 pins are pulled down by an internal 2 MΩ weak pull-downs to prevent the
pins from floating. Thus the dimming control input pins are default to 'LED OFF' state and need external pulled
up resistors when the pins are connected to open collector/drain signal sources. Figure 13 shows a suggested
circuit for connecting the LM3463 to an open collector/drain dimming signal sources.
LM3463
External PWM
signal source R_PU
(e.g. MCU) 47 k
Open-drain output
O/P
VCC
DIMn
BUF
2M
PWM
signal
VCC
Regulator
BUF
To dimming
control
circuit
GND
GND
GND
Figure 13. Adding an external pull-up resistor to the DIMn pin
Direct PWM Dimming Mode
Connecting the MODE pin to ground enables direct PWM dimming mode. Every dimming control pin (DIM01 to
DIM5) in direct PWM control mode accepts active high TTL logic level signal. In direct PWM dimming mode, the
six output channels are separated into four individual groups to accept external PWM dimming signals. The
configuration of output channels are as listed in the following table:
Group A
Group B
Group C
Group D
CH0 and CH1, controlled by DIM01 pin
CH2 and CH3, controlled by DIM23 pin
CH4, controlled by DIM4 pin
CH5, controlled by DIM5 pin
In order to secure accurate current regulation, the pull-up time of every dimming control input must not be shorter
than 8 µs. If a 256 level (8-bit resolution) brightness control is needed, the PWM dimming frequency should be
no higher than 488Hz.
Serial Interface Mode
Leaving MODE pin floating enables serial interface mode. In serial interface mode, the DIM01, DIM23 and DIM4
pins are used together as a serial data interface to accept external dimming control data frames serially. The
following table presents the functions of the DIM01, DIM23 and DIM4 pins in serial interface mode:
DIM01
DIM23
DIM4
Serial data packet input (8-bit packet size)
Clock signal input for data bit latching
End Of Frame (EOF) signal input for data packet loading
The DIM5 pin is not used in this mode and should connect to GND. Every data frame contains four 8–bit wide
data byte for PWM dimming control. Every data byte controls the PWM dimming duty of its corresponding output
channel(s): A hexadecimal 000h gives 0% dimming duty; a hexadecimal 0FFh gives 100% dimming duty.
Respectively, the first byte being loaded into the LM3463 controls the dimming duty of CH0 and CH1, the second
byte controls the dimming duty of CH2 and CH3, the third byte controls the dimming duty of CH4 and the forth
byte controls the dimming duty of CH5.
In serial interface mode, the six output channels are separated into four individual groups as listed in the
following table:
Group A
CH0 and CH1, controlled by the first byte
Copyright © 2012, Texas Instruments Incorporated
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