TMS320DM6433_17 Datasheet, PDF (241/271 Pages) Texas Instruments – Digital Media Processor

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6.16.2 EMAC Electrical Data/Timing
TMS320DM6433
Digital Media Processor
SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-69. Timing Requirements for MRCLK (see Figure 6-39)
NO.
1 t_c(MRCLK) Cycle time, MRCLK
2 t_w(MRCLKH) Pulse duration, MRCLK high
3 t_w(MRCLKL) Pulse duration, MRCLK low
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
10 Mbps 100 Mbps
MIN MAX MIN MAX
400
40
140
14
140
14
UNIT
ns
ns
ns
1
2
3
MRCLK
Figure 6-39. MRCLK Timing (EMAC - Receive)
Table 6-70. Timing Requirements for MTCLK (see Figure 6-39)
NO.
1 t_c(MTCLK) Cycle time, MTCLK
2 t_w(MTCLKH) Pulse duration, MTCLK high
3 t_w(MTCLKL) Pulse duration, MTCLK low
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
10 Mbps 100 Mbps
MIN MAX MIN MAX
400
40
140
14
140
14
UNIT
ns
ns
ns
1
2
3
MTCLK
Figure 6-40. MTCLK Timing (EMAC - Transmit)
Table 6-71. Timing Requirements for EMAC MII Receive 10/100 Mbit/s⁽¹⁾ (see Figure 6-41)
NO.
1 t_{su(MRXD-MRCLKH)}
Setup time, receive selected signals valid before MRCLK high
2 t_{h(MRCLKH-MRXD)}
Hold time, receive selected signals valid after MRCLK high
(1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
-7/-6/-5/-4
-L/-Q6/-Q5/-
Q4
MIN MAX
8
8
UNIT
ns
ns
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Peripheral Information and Electrical Specifications 241