TMS320DM6433_17 Datasheet, PDF (1/271 Pages) Texas Instruments – Digital Media Processor

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1 TMS320DM6433 Digital Media Processor
TMS320DM6433
Digital Media Processor
SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008
1.1 Features
• High-Performance Digital Media Processor
(DM6433)
– 2.5-, 2-, 1.67-, 1.51-, 1.43-ns ns Instruction
Cycle Time
– 400-, 500, -600-, 660-, 700-MHz C64x+™
Clock Rate
– Eight 32-Bit C64x+ Instructions/Cycle
– 3200, 4000, 4800, 5280, 5600 MIPS
– Fully Software-Compatible With C64x
– Commercial and Automotive (Q or S suffix)
Grades
– Low-Power Device (L suffix)
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Auto-Focus Module Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support
Complex Multiplies
• C64x+ L1/L2 Memory Architecture
– 256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
– 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
– 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
• Supports Little Endian Mode Only
• Video Processing Subsystem (VPSS)
– Front End Provides (Resizer Only):
• Resize Images From 1/4x to 4x
• Separate Horizontal and Vertical Control
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Four 54-MHz DACs for a Combination of
– Composite NTSC/PAL Video
– Luma/Chroma Separate Video
(S-video)
– Component (YPbPr or RGB) Video
(Progressive)
• Digital Output
– 8-/16-bit YUV or up to 24-Bit RGB
– HD Resolution
– Up to 2 Video Windows
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
• Supports up to 333-MHz (data rate) bus
and interfaces to DDR2-400 SDRAM
– Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
• Flash Memory Interfaces
– NOR (8-Bit-Wide Data)
– NAND (8-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• One UART With RTS and CTS Flow Control
• Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• One Multichannel Buffered Serial Port
(McBSP0)
– I2S and TDM
– AC97 Audio Codec Interface
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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