ADS6445-EP_13 Datasheet, PDF (24/66 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445-EP
ADS6444-EP
SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
www.ti.com
NAME
PINS
INB_P, INB_M
NO.
15, 14
INC_P, INC_M
34, 35
IND_P, IND_M
CAP
37, 38
5
SCLK
44
SDATA
43
SEN
42
RESET
PDN
CFG1
CFG2
CFG3
CFG4
VCM
OUTPUT PINS
DA0_P,DA0_M
DA1_P,DA1_M
DB0_P,DB0_M
DB1_P,DB1_M
DC0_P,DC0_M
DC1_P,DC1_M
DD0_P,DD0_M
DD1_P,DD1_M
DCLKP,DCLKM
FCLKP,FCLKM
NC
PAD
6
41
30
29
28
21
22
3, 4
1, 2
62, 63
60, 61
52, 53
50, 51
47, 48
45, 46
57, 58
55, 56
20
0
PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)
I/O
NO. OF
PINS
DESCRIPTION
I
2
Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do not
float.
I
2
Differential input signal pair, channel C If unused, the pins should be tied to VCM. Do not
float.
I
2
Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do not
float.
1
Connect 2-nF capacitor from pin to ground
This pin functions as serial interface clock input when RESET is low.
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SDATA). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface data input when RESET is low.
I
1
When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes (along
with SCLK). Refer to Table 5 for description.
This pin has an internal pull-down resistor.
This pin functions as serial interface enable input when RESET is low.
I
1
When RESET is high, it controls coarse gain and internal/external reference modes. Refer to
Table 6 for description.
This pin has an internal pull-up resistor.
Serial interface reset input.
When using the serial interface mode, the user MUST initialize internal registers through
I
1
hardware RESET by applying a high-going pulse on this pin or by using software reset
option. Refer to the Serial Interface section. In parallel interface mode, tie RESET
permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode).
The pin has an internal pull-down resistor to ground.
I
1
Global power down control pin.
Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock selection.
I
1
Refer to Table 8 for description.
Tie to AVDD for 2-wire interface with DDR bit clock.
Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge. Refer to
I
1
Table 9 for description.
For 14x serialization with DDR bit clock, tie to ground or AVDD.
I
1
RESERVED pin - Tie to ground.
I
1
Parallel input pin. It controls data format and MSB or LSB first modes. Refer to Table 11 for
description.
Internal reference mode – common-mode voltage output
I/O
1
External reference mode – reference input. The voltage forced on this pin sets the internal
reference.
O
2
Channel A differential LVDS data output pair, wire 0
O
2
Channel A differential LVDS data output pair, wire 1
O
2
Channel B differential LVDS data output pair, wire 0
O
2
Channel B differential LVDS data output pair, wire 1
O
2
Channel C differential LVDS data output pair, wire 0
O
2
Channel C differential LVDS data output pair, wire 1
O
2
Channel D differential LVDS data output pair, wire 0
O
2
Channel D differential LVDS data output pair, wire 1
O
2
Differential bit clock output pair
O
2
Differential frame clock output pair
1
Do Not Connect
1
Connect to ground plane using multiple vias. Refer to Board Design Considerations section.
24
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