ADS6445-EP_13 Datasheet, PDF (22/66 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445-EP
ADS6444-EP
SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
www.ti.com
10000
00101
500 Ω
Any combination of above bits also can be programmed, resulting in a parallel combination of
the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
REGISTER
ADDRESS
A4 - A0
11
D4-D0
00000
00001
00010
00100
01000
10000
00101
Table 20. Serial Register H
BITS
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
WORD-WISE CONTROL
0
0
0
0
<TERM DATA>
LVDS INTERNAL TERMINATION - DATA OUTPUTS
<TERM DATA> LVDS internal termination for data outputs
No internal termination
166 Ω
200 Ω
250 Ω
333 Ω
500 Ω
Any combination of above bits can also be programmed, resulting in a parallel combination
of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω
100 Ω
D10-D9
00
11
01,10
Only when 2-wire interface is selected
Byte-wise or bit-wise output, 1x frame clock
Word-wise output enabled, 0.5x frame clock
Do not use
22
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