ADS6445-EP_13 Datasheet, PDF (18/66 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445-EP
ADS6444-EP
SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
DESCRIPTION OF SERIAL REGISTERS
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Table 13. Serial Register A
REGISTER
ADDRESS
A4 - A0
D10
D9
D8
D7
00
<RST>
S/W RESET
0
0
0
D0 - D4
Power down modes
BITS
D6
D5
D4
D3
D2
D1
0
<REF>
INTERNAL
OR
EXTERNAL
<PDN CHD> <PDN CHC> <PDN CHB> <PDN CHA>
POWER
POWER
POWER
POWER
DOWN CH D DOWN CHC DOWN CH B DOWN CH A
D0
<PDN>
GLOBAL
POWER
DOWN
D0
<PDN GLOBAL>
0
Normal operation
1
Global power down, including all channels ADCs, internal references, internal PLL and output
buffers
D1
<PDN CHA>
0
CH A Powered up
1
CH A ADC Powered down
D2
<PDN CHB>
0
CH B Powered up
1
CH B ADC Powered down
D3
<PDN CHC>
0
CH C Powered up
1
CH C ADC Powered down
D4
<PDN CHD>
0
CH D Powered up
1
CH D ADC Powered down
D5
<REF> Reference
0
Internal reference enabled
1
External reference enabled
D10
<RST>
1
Software reset applied – resets all internal registers and self-clears to 0
18
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