ADS6445-EP_13 Datasheet, PDF (1/66 Pages) Texas Instruments – QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS

ADS6445-EP
ADS6444-EP
www.ti.com
SLAS573C – FEBRUARY 2008 – REVISED MAY 2013
QUAD CHANNEL, 14 BIT, 125/105 MSPS ADC WITH SERIAL LVDS OUTPUTS
Check for Samples: ADS6445-EP, ADS6444-EP
FEATURES
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• Maximum Sample Rate: 125 MSPS
• 14-Bit Resolution with No Missing Codes
• Simultaneous Sample and Hold
• 3.5-dB Coarse Gain and up to 6-dB
Programmable Fine Gain for SFDR/SNR Trade-
Off
• Serialized LVDS Outputs with Programmable
Internal Termination Option
• Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude Down to 400 mV_PP
• Internal Reference with External Reference
Support
• No External Decoupling Required for
References
• 3.3-V Analog and Digital Supply
• 64-pin QFN Package (9 mm × 9 mm)
• Feature Compatible Dual Channel Family
APPLICATIONS
• Base-Station IF Receivers
• Diversity Receivers
• Medical Imaging
• Test Equipment
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly and Test Site
• One Fabrication Site
• Available in Military (–55°C to 125°C)
Temperature Range
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
Table 1. ADS644X Quad Channel Family⁽¹⁾
ADS644X
14 Bit
125 MSPS
ADS6445
105 MSPS
ADS6444
(1) Product Preview for ADS6444
SFDR, dBc
SINAD, dBFS
Table 2. Performance Summary
Fin = 10 MHz (0 dB gain)
Fin = 170 MHz (3.5 dB gain)
Fin = 10 MHz (0 dB gain)
Fin = 170 MHz (3.5 dB gain)
Power, per channel, mW
ADS6445
87
79
73.4
68.3
420
ADS6444
91
83
73.4
69.3
340
DESCRIPTION
The ADS6445/ADS6444 is a high performance 14 bit 125/105 MSPS quad channel A-D converter. Serial LVDS
data outputs reduce the number of interface lines, resulting in a compact 64-pin QFN package (9 mm × 9 mm)
that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to
improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also
exist, programmable in 1 dB steps up to 6 dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing
receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and
bit clocks also are transmitted as LVDS outputs.
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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