OMAP3530_14 Datasheet, PDF (236/266 Pages) Texas Instruments – Applications Processors

OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode^{(1) (2) (3)} (continued)
NO.
PARAMETER
HSSD3/SD3 t_{su(CMDV-CLKIH)}
HSSD4/SD4 t_{su(CLKIH-CMDIV)}
MMC/SD/SDIO Interface 3
HSSD3/SD3 t_{su(CMDV-CLKIH)}
HSSD4/SD4 t_{su(CLKIH-CMDIV)}
Setup time, mmc2_cmd valid before
mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after
mmc2_clk rising clock edge
Setup time, mmc3_cmd valid before
mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after
mmc3_clk rising clock edge
1.15 V
MIN
MAX
1198.4
1249.2
1.0 V
MIN
MAX
1198.4
1249.2
UNIT
ns
ns
1198.4
1198.4
ns
1249.2
1249.2
ns
Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode⁽¹⁾
NO.
PARAMETER
SD Identification Mode
1/
1/t_c(clk)
(HSSD1/SD1
)
Frequency⁽²⁾, mmcx_ clk ⁽³⁾
HSSD2/SD2 t_W(clkH)
Typical pulse duration, output clk high
HSSD2/SD2 t_W(clkL)
Typical pulse duration, output clk low
t_dc(clk)
t_j(clk)
Duty cycle error, output clk
Jitter standard deviation⁽⁷⁾, output clk
MMC/SD/SDIO Interface 1 (1.8 V IO)
HSSD5/SD5
t_c(clk)
t_W(clkH)
t_W(clkL)
t_dc(clk)
t_d(CLKOH-CMD)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
MMC/SD/SDIO Interface 1 (3.0 V IO)
HSSD5/SD5
t_c(clk)
t_W(clkH)
t_W(clkL)
t_dc(clk)
t_d(CLKOH-CMD)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
MMC/SD/SDIO Interface 2
HSSD5/SD5
t_c(clk)
t_W(clkH)
t_W(clkL)
t_dc(clk)
t_d(CLKOH-CMD)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
MMC/SD/SDIO Interface 3
t_c(clk)
Rise time, output clk
1.15 V
MIN
MAX
0.4
X ⁽⁴⁾*PO ⁽⁵⁾
Y ⁽⁶⁾*PO⁽⁵⁾
125
200
10
10
10
10
6.3
2492.7
1.0 V
MIN
MAX
0.4
UNIT
MHz
X ⁽⁴⁾*PO ⁽⁵⁾
ns
Y ⁽⁶⁾*PO ⁽⁵⁾
ns
125
ns
200
ps
10
ns
10
ns
10
ns
10
ns
6.3
2492.7
ns
10
0
ns
10
0
ns
10
10
ns
10
10
ns
6.3
2492.7
6.3
2492.7
ns
10
10
ns
10
10
ns
10
10
ns
10
10
ns
6.3
2492.7
6.3
2492.7
ns
10
10
ns
(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(3) In mmcx_clk, 'x' is equal to 1, 2, or 3.
(4) The X parameter is defined as shown in Table 6-120.
(5) PO = output clk period in ns.
(6) The Y parameter is defined as shown in Table 6-121.
(7) The jitter probability density can be approximated by a Gaussian function.
236 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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