OMAP3530_14 Datasheet, PDF (169/266 Pages) Texas Instruments – Applications Processors

OMAP3530, OMAP3525
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GPMC_FCLK
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
FA21
FA9
FA10
Add0
FA10
FA12
FA13
FA20
FA1
FA20 FA20
Add1 Add2 Add3
FA0
Add4
FA0
FA18
D0
D1 D2
D3
D3
gpmc_waitx
FA15
gpmc_io_dir
OUT ^FA14
IN
OUT
030-028
Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1) (2) (3) (4)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside AccessTime register bit field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge
after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input
page data). FA20 value must be stored in PageBurstAccessTime register bit field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 169
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