OMAP3530_14 Datasheet, PDF (202/266 Pages) Texas Instruments – Applications Processors

OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
6.6 Serial Communications Interfaces
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing
There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct
serial interface between the OMAP3530/25 device and other devices in a system such as other
application devices or codecs. It can accommodate a wide range of peripherals and clocked frame-
oriented protocols (I2S, PCM, and TDM) due to its high level of versatility.
The McBSP1-5 modules may support two types of data transfer at the system level:
• The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
• The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
The OMAP3530/25 McBSP1-5 timing characteristics are described for both rising and falling activation
edges. McBSP1 supports:
• 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
• 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back via software configuration, respectively, to the clkr and fsr internal signals for
data receive.
McBSP2, 3, 4, and 5 support only the 4-pin mode.
The following sections describe the timing characteristics for applications in normal mode (that is,
OMAP3530/25 McBSPx connected to one peripheral) and TDM applications in multipoint mode.
6.6.1.1 McBSP in Normal Mode
Table 6-42. McBSP Timing Conditions—Normal Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
C_LOAD
Output load capacitance
VALUE
2
2
10
UNIT
ns
ns
pF
Table 6-43. McBSP Output Clock Pulse Duration
NO.
PARAMETER
Inputs and Outputs
McBSP1 t_c(CLK)
Cycle time, mcbsp1_clkx / mcbsp1_clkr (multiplexing mode
0)
McBSP2 t_c(CLK)
McBSP3 t_c(CLK)
Cycle time, mcbsp2_clkx (multiplexing mode 0)
Cycle time,
mcbsp3_clkx
IO set 1 (multiplexing mode 0)
IO set 2 (multiplexing mode 1)
IO set 3 (multiplexing mode 2)
McBSP4 t_c(CLK)
Cycle time,
mcbsp4_clkx
IO set 1 (multiplexing mode 0)
IO set 2 (multiplexing mode 2)
McBSP5 t_c(CLK)
Cycle time, mcbsp5_clkx (multiplexing mode 1)
OPP3
MIN
MAX
20.83
20.83
31.25
20.83
20.83
20.83
31.25
31.25
OPP2
MIN
MAX
41.67
41.67
62.50
41.67
41.67
41.67
62.50
62.50
UNIT
ns
ns
ns
ns
ns
202 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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