OMAP3530_14 Datasheet, PDF (188/266 Pages) Texas Instruments – Applications Processors

OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 6-25. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode (continued)
TIMING CONDITION PARAMETER
Output Conditions
C_LOAD
Output load capacitance
VALUE
8.6
UNIT
pF
Table 6-26. ISP Timing Requirements – 8-bit Packed SYNC – Progressive Mode⁽¹⁾
NO.
PARAMETER
1.15 V
ISP3
ISP4
ISP4
ISP5
t_c(pclk)
t_W(pclkH)
t_W(pclkL)
t_dc(pclk)
t_j(pclk)
t_su(dV-pclkH)
Cycle time⁽²⁾, cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
Cycle jitter⁽⁴⁾, cam_pclk
Setup time, cam_d[11:0] valid before cam_pclk
rising edge
MIN
MAX
7.7
0.5*P ⁽³⁾
0.5*P ⁽³⁾
385
83
1.08
ISP6
t_h(pclkH-dV)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
1.08
ISP7
t_su(dV-vsH)
Setup time, cam_vs valid before cam_pclk rising
edge
1.08
ISP8
ISP9
t_h(pclkH-vsV)
t_su(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
Setup time, cam_hs valid before cam_pclk rising
edge
1.08
1.08
ISP10
ISP11
t_h(pclkH-hsV)
t_su(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
Setup time, cam_wen valid before cam_pclk rising
edge
1.08
1.08
ISP12 t_h(pclkH-hsV)
Hold time, cam_wen valid after cam_pclk rising edge 1.08
(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(2) Related with the input maximum frequency supported by the ISP module.
(3) P = cam_pclk period in ns.
(4) Maximum cycle jitter supported by cam_pclk input clock.
1.0 V
MIN
MAX
15.4
0.5*P ⁽³⁾
0.5*P ⁽³⁾
769
167
2.27
2.27
2.27
2.27
2.27
2.27
2.27
2.27
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-27. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
ISP1
ISP2
ISP2
t_c(xclk)
t_W(xclkH)
t_W(xclkL)
t_dc(xclk)
t_j(xclk)
t_R(xclk)
t_F(xclk)
Cycle time⁽¹⁾, cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
Jitter standard deviation⁽³⁾, cam_xclk
Rise time, cam_xclk
Fall time, cam_xclk
MIN
MAX
MIN
MAX
4.6
4.6
ns
0.5*PO ⁽²⁾
0.5*PO ⁽²⁾
ns
0.5*PO ⁽²⁾
0.5*PO ⁽²⁾
ns
231
231
ps
67
67
ps
0.93
0.93
ns
0.93
0.93
ns
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see
the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]
(2) PO = cam_xclk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
188 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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