LMH7220_14 Datasheet, PDF (23/34 Pages) Texas Instruments – LMH7220 High Speed Comparator with LVDS Output

LMH7220
www.ti.com
SNOSAL3E – SEPTEMBER 2006 – REVISED MAY 2013
LOADING THE OUTPUT
The output structure creates a current (I_LOOP see Figure 32) through an external differential load resistor of 100Ω
nominal. This results in a differential output voltage of 325 mV. The outputs of the comparator are connected to
tracks on a PCB. These tracks can be seen as a differential transmission line. The differential load resistor acts
as a high frequency termination at the end of the transmission line. This means that for a proper signal behavior
the PCB tracks have to be dimensioned for a characteristic impedance of 100Ω as well. Changing the load
resistor also implies a change of the transmission line impedance. More about transmission lines and termination
can be found in the next section. The signal across the 100Ω termination resistor is fed into the inputs of
subsequent circuitry that processes the data. Any connection to input circuitry of course draws current from the
comparator’s outputs. In the case of a balanced input connected to the load resistance, current I_P is drawn from
both output connection points to ground. Keep in mind that the LMH7220’s ability to source currents is much
higher than to sink them. The connected input circuitry also forms a differential load to the outputs of the
comparator (see Figure 32). This will cause the voltage across the termination resistor to differ from its nominal
value.
I_P
VCC
IN+
+ OUT Q
- ^{OUT Q}
IN-
C_P
R_P
I_LOOP
R_LOAD
C_LOAD
GND
LOAD
R_P
C_P
I_P
Figure 32. Load
In general one single connection only draws a few µA’s, and doesn’t have much effect on the LVDS output
voltage. For multiple inputs on one output pair, load currents must not exceed the specified limits, as described in
the ANSI or IEEE LVDS standards. Below a specified value of V_OD, the functioning of subsequent circuitry
becomes uncertain. However under normal conditions there is no need to worry. Another point of practice is load
capacitances. Capacitances are applied differentially (C_LOAD) and also to ground (C_P). All of these capacitors will
disturb the pulse shape. The edges of the output pulse become slower, and in reaction the detection of the
transition comes at a later moment. Be aware of this effect when measuring with probes. Both single ended and
differential probes have these capacitances. A standard probe commonly has a load capacity of about 8 to 10
pF. This will cause some degradation of the pulse shape and will add some time delay.
TRANSMISSION LINES & TERMINATION TECHNOLOGIES
The LMH7220 uses LVDS technology. LVDS is a way to communicate data using low voltage swing and low
power consumption. Nowadays data rates are growing, requiring increasing speed. Data isn’t only connected to
other IC’s on a single PCB board but in many cases there are interconnections from board to board or from
equipment to equipment. Distances can be short or long but it is always necessary to have a reliable connection,
consume low power and to be able to handle high data rates. LVDS is a differential signal protocol. The
advantage over single ended signal transmission is its higher immunity to common mode noise. Common mode
signals are signals that are equally apparent on both lines and because the receiver only looks at the difference
between both lines, this noise is canceled.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH7220
Submit Documentation Feedback
23