LMH7220_14 Datasheet, PDF (13/34 Pages) Texas Instruments – LMH7220 High Speed Comparator with LVDS Output

LMH7220
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SNOSAL3E – SEPTEMBER 2006 – REVISED MAY 2013
APPLICATION INFORMATION
INTRODUCTION
The LMH7220 is a high speed comparator with LVDS outputs. The LVDS (Low Voltage Differential Signaling)
standard uses differential outputs with a voltage swing of approximately 325 mV on each output. The most widely
used setup for LVDS outputs consists of a switched current source of 3.25 mA. The output pins need to be
differentially terminated with an external 100Ω resistor, producing the standardized output voltage swing of 325
mV. The common mode level of both outputs is about 1.2V, and is independent of the power supply voltage. The
use of complementary outputs gives a high level of suppression for common mode noise. The very fast rise and
fall times of the LMH7220 enable data transmission rates up to several hundreds of Megabits per second (Mbps).
Due to the current-nature of the outputs the power consumption remains at a very low level even if the data
transmission rate is rising. Power delivered to a load resistance of 100Ω is only 1.2 mW.
The LMH7220 inputs have a common mode voltage range that extends 200 mV below the negative supply
voltage thus allowing ground sensing in case of single supply. The rise and fall times of the LMH7220 are about
0.6 ns, while the propagation delay time is about 2.7 ns. The LMH7220 can operate over the full supply voltage
range of 2.7V to 12V, while using single or dual supply voltages. The LVDS outputs refer to the negative supply
rail. The supply current is 6.8 mA at 5V (load current excluded). The LMH7220 is available in the 6-Pin SOT
package.
In the next sections the following issues are discussed:
• In- and output topology
• Definition of terms of used specifications
• Propagation delay and dispersion
• Hysteresis and oscillations
• The output
• Applying transmission lines
• PCB layout
INPUT & OUTPUT TOPOLOGY
All input and output pins are protected against excessive voltages by ESD diodes. These diodes are connected
from the negative supply to the positive supply. As can be seen in Figure 19, both inputs are connected to these
diodes. Protection against excessive supply voltages is provided by a power clamp between V_CC and GND. Both
inputs are also connected to the bases of the input transistors of the differential pair via 1.5 kΩ resistors. The
input transistors cannot withstand high reverse voltages between bases and emitter, due to their high frequency
properties. To protect the input stage against damage, both bases are connected together by a string of anti-
parallel diodes. Be aware of situations in which differential input voltage level is such that these diodes are
conducting. In this case the input current is raised far above the normal value stated in the datasheet tables.
VCC
VCC
1.5 k:
IN+
VCC
VCC
1.5 k:
IN-
Power
Clamp
Equivalent Input Circuitry
Figure 19. Equivalent Input Circuitry
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