LMH7220_14 Datasheet, PDF (14/34 Pages) Texas Instruments – LMH7220 High Speed Comparator with LVDS Output

LMH7220
SNOSAL3E – SEPTEMBER 2006 – REVISED MAY 2013
www.ti.com
The output can be seen as a bridge configuration in which switches are crosswise closed, producing the
differential LVDS logic high and low levels (see Figure 20). The output switches are fed at top and bottom by two
current sources. The top one is fixed and determines the differential voltage across the external load resistor.
The other one is regulated and determines the common-mode voltage on the outputs. It is essential to keep the
output common-mode voltage at the defined standardized LVDS level under all circumstances. To realize this,
both outputs are internally connected together via two equal resistors. At the midpoint this produces the common
mode output voltage, which is made equal to V_REF (1.2V) by means of the CM feedback loop.
VCC
Current 3.25 mA
Output Q
Current 3.25 mA
Output Q
+
-
CM loop
V_REF
+
-
Equivalent Output Circuitry
Figure 20. Equivalent Output Circuitry
DEFINITIONS
For a good understanding of many parameters of the LMH7220 it is necessary to perform a lot of measurements.
All of those parameters are listed in the data tables in the first part of the datasheet. There are different tables for
several supply voltages containing a separate set of data per supply voltage. In the table below is a list of
abbreviations of the measured parameters and a short description of the conditions which are applied for
measuring them . Following this table several parameters are highlighted to explain more clearly what it means
exactly and what effects such a phenomena can have for any applied electronic circuit.
Symbol
I_B
I_OS
TC I_OS
V_OS
TC V_OS
CMRR
VRI
PSRR
V_O
Text
Input Bias Current
Input Offset Current
Average Input Offset Current Drift
Input Offset Voltage
Average Input Offset Voltage Drift
Common Mode Rejection Ratio
Input Voltage Range
Power Supply Rejection Ratio
Output Offset Voltage
Description
Current flowing in or out the input pins, when both biased at 0.3 Volt above
GND
Difference between the positive- and the negative input currents needed to
make the outputs change state, averaged for H to L and L to H transitions
Temperature Coefficient of I_OS
Voltage difference needed between IN⁺ and IN^− to make the outputs
change state, averaged for H to L and L to H transitions
Temperature Coefficient of V_OS
Ratio of input offset voltage change and input common mode voltage
change
Upper and lower limits of the input voltage are defined as where CMRR
drops below 50 dB.
Ratio of input offset voltage change and supply voltage change from V_S-MIN
to V_S-MAX
Output Common Mode Voltage averaged for logic ‘0’ and logic ‘1’ levels
(See Figure 30)
14
Submit Documentation Feedback
Product Folder Links: LMH7220
Copyright © 2006–2013, Texas Instruments Incorporated