LMH7220_14 Datasheet, PDF (15/34 Pages) Texas Instruments – LMH7220 High Speed Comparator with LVDS Output

LMH7220
www.ti.com
SNOSAL3E – SEPTEMBER 2006 – REVISED MAY 2013
Symbol
ΔV_O
V_OH
V_OL
V_ODH
V_ODL
V_OD
ΔV_OD
Hyst
I_SQG, I_SQG
I_SQQ
TR
PW
t_PDH resp t_PDL
t_PDLresp t_PDH
t_PDLH
t_PDHL
t_PD
t_PDHd resp t_PDLd
Δt_PDLH resp Δt_PDHL
Δt_PD
Δt_PDd
t_OD-disp
t_SR-disp
t_CM-disp
t_r / t_rd
t_f / t_fd
Text
Change in Output Offset Voltage
Output Voltage High
Output Voltage Low
Output Differential Voltage logic ‘1’
Output Differential Voltage logic ‘0’
Average of V_ODH and V_ODL
Change in V_OD between ‘0’ and ‘1’
Hysteresis
Short Circuit Current one output to GND
Short Circuit Current outputs together
Maximum Toggle Rate
Pulse Width
Propagation Delay
Q to Q time skew
Average Q to Q time skew
Average diff. time skew
Input overdrive dispersion
Input slew rate dispersion
Input Common Mode dispersion
Output rise time (20% - 80%)
Output fall time (20% - 80%)
Description
Difference in Output Common Mode Voltage between logic ‘0’ and logic ‘1’
levels (See Figure 31)
High state single ended output voltage (Q or Q) (See Figure 30)
Low state single ended output voltage (Q or Q) (See Figure 30)
V_OH(Q) – V_OL(Q) (logic level ‘1’) (See Figure 31)
V_OH(Q) – V_OL(Q) (logic level ‘0’) (See Figure 31)
(V_ODH + V_ODL) / 2
|V_ODH – V_ODL| (See Figure 31)
Difference in input switching levels for L to H and H to L transitions. (See
Figure 29)
Current that flows from one output to GND if shorted single ended
Current flowing between output Q and output Q if shorted differentially
Maximum frequency at which the outputs can toggle before V_OD drops
under 50% of the nominal value.
Time from 50% of the rising edge of a signal to 50% of the falling edge
Delay time between the moment the input signal crosses the switching
level L to H and the moment the output signal crosses 50% of the rising
edge of Q output (t_PDH), or delay time between the moment the input signal
crosses the switching level H to L and the moment the output signal
crosses 50% of the falling edge of Q output (t_PDL)
Delay time between the moment the input signal crosses the switching
level L to H and the moment the output signal crosses 50% of the falling
edge of Q output (t_PDL), or delay time between the moment the input signal
crosses the switching level H to L and the moment the output signal
crosses 50% of the rising edge of Q output (t_PDH)
Average of t_PDH and t_PDL
Average of t_PDL and t_PDH
Average of t_PDLH and t_PDHL
Delay time between the moment the input signal crosses the switching
level L to H and the zero crossing of the rising edge of the differential
output signal (t_PDHd), or delay time between the moment the input signal
crosses the switching level H to L and the zero crossing of the falling edge
of the differential output signal (t_PDLd)
Time skew between 50% levels of rising edge of Q output and falling edge
of Q output (Δt_PDLH ), or time skew between 50% levels of falling edge of Q
output and rising edge of Q output (Δt_PDHL)
Average of t_PDLH and t_PDHL for L to H and H to L transients
Average of t_PDHd and t_PDLd for L to H and H to L transients
Change in t_PD for different overdrive voltages at the input pins
Change in t_PD for different slew rates at the input pins
Change in t_PD for different common mode voltages at the input pins
Time needed for the (single ended or differential) output voltage to change
from 20% of its nominal value to 80%
Time needed for the (single ended or differential) output voltage to change
from 80% of its nominal value to 20%
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