AM3359_017 Datasheet, PDF (226/253 Pages) Texas Instruments – Sitara Processors

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
DATAIN
1
2
4
3
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Figure 7-100. PRU-ICSS PRU Shift In Timing
Table 7-96. PRU-ICSS PRU Switching Requirements - Shift Out Mode
(see Figure 7-101)
NO.
MIN
MAX
1
t_c(CLOCKOUT)
2
t_w(CLOCKOUT)
3
t_r(CLOCKOUT)
4
t_f(CLOCKOUT)
5
t_{d(CLOCKOUT-DATAOUT)}
6
t_r(DATAOUT)
t_f(DATAOUT)
Cycle time, CLOCKOUT
Pulse width, CLOCKOUT
Rising time, CLOCKOUT
Falling time, CLOCKOUT
Delay time, CLOCKOUT to DATAOUT valid
Rising time, DATAOUT
Falling time, DATAOUT
10.00
0.45 × P⁽¹⁾
1.00
1.00
0.00
1.00
1.00
0.55 × P⁽¹⁾
3.00
3.00
3.00
3.00
3.00
(1) P = L3_CLK (PRU-ICSS ocp clock) period.
UNIT
ns
ns
ns
ns
ns
ns
ns
1
2
4
3
CLOCKOUT
DATAOUT
5
6
Figure 7-101. PRU-ICSS PRU Shift Out Timing
7.14.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
Table 7-97. PRU-ICSS ECAT Timing Conditions
PARAMETER
MIN
Output Condition
C_load
Capacitive load for each bus line
7.14.2.1 PRU-ICSS ECAT Electrical Data and Timing
MAX UNIT
30
pF
Table 7-98. PRU-ICSS ECAT Timing Requirements – Input Validated with LATCH_IN
(see Figure 7-102)
NO.
MIN
MAX
1
t_{w(EDIO_LATCH_IN)}
2
t_{r(EDIO_LATCH_IN)}
3
t_{f(EDIO_LATCH_IN)}
4
t_{su(EDIO_DATA_IN-}
EDIO_LATCH_IN)
5
t_{h(EDIO_LATCH_IN-}
EDIO_DATA_IN)
Pulse width, EDIO_LATCH_IN
Rising time, EDIO_LATCH_IN
Falling time, EDIO_LATCH_IN
Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN
active edge
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active
edge
100.00
1.00
3.00
1.00
3.00
20.00
20.00
UNIT
ns
ns
ns
ns
ns
226 Peripheral Information and Timings
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