AM3359_017 Datasheet, PDF (137/253 Pages) Texas Instruments – Sitara Processors

www.ti.com
AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
Table 7-25. GPMC and NOR Flash Timing Requirements—Asynchronous Mode
NO.
OPP100
OPP50
UNIT
FA5⁽¹⁾
FA20⁽²⁾
FA21⁽³⁾
t_acc(d)
t_{acc1-pgmode(d)}
t_{acc2-pgmode(d)}
Data access time
Page mode successive data access time
Page mode first data access time
MIN
MAX
H⁽⁵⁾
P⁽⁴⁾
H⁽⁵⁾
MIN
MAX
H⁽⁵⁾
ns
P⁽⁴⁾
ns
H⁽⁵⁾
ns
(1) The FA5 parameter shows the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter shows amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter shows amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾
(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
NO.
FA0
FA1
FA3
FA4
FA9
FA10
FA12
FA13
FA16
FA18
FA20
FA25
Table 7-26. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
t_R(d)
t_F(d)
t_w(be[x]nV)
t_w(csnV)
t_{d(csnV-advnIV)}
t_{d(csnV-oenIV)}
t_d(aV-csnV)
t_{d(be[x]nV-csnV)}
t_{d(csnV-advnV)}
t_d(csnV-oenV)
t_w(aIV)
t_{d(csnV-oenIV)}
t_w(aV)
t_d(csnV-wenV)
PARAMETER
Rise time, output data gpmc_ad[15:0]
Fall time, output data gpmc_ad[15:0]
Pulse duration, output lower-byte
enable and command latch enable
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
Read
Write
Pulse duration, output chip select
gpmc_csn[x]⁽¹³⁾ low
Read
Write
Delay time, output chip select
gpmc_csn[x]⁽¹³⁾ valid to output
address valid and address latch
enable gpmc_advn_ale invalid
Read
Write
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output enable gpmc_oen invalid (Single
read)
Delay time, output address gpmc_a[27:1] valid
to output chip select gpmc_csn[x]⁽¹³⁾ valid
Delay time, output lower-byte enable and
command latch enable gpmc_be0n_cle, output
upper-byte enable gpmc_be1n valid to output
chip select gpmc_csn[x]⁽¹³⁾ valid
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output address valid and address latch
enable gpmc_advn_ale valid
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output enable gpmc_oen valid
Pulse durationm output address gpmc_a[26:1]
invalid between 2 successive read and write
accesses
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output enable gpmc_oen invalid (Burst
read)
Pulse duration, output address gpmc_a[27:1]
valid - 2nd, 3rd, and 4th accesses
Delay time, output chip select gpmc_csn[x]⁽¹³⁾
valid to output write enable gpmc_wen valid
OPP100
MIN
MAX
2
2
N⁽¹²⁾
N⁽¹²⁾
B⁽²⁾ – 0.2
B⁽²⁾ – 0.2
A⁽¹⁾
A⁽¹⁾
B⁽²⁾ + 2.0
B⁽²⁾ + 2.0
C⁽³⁾ – 0.2 C⁽³⁾ + 2.0
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.0
J⁽⁹⁾ – 0.2 J⁽⁹⁾ + 2.0
K⁽¹⁰⁾ – 0.2 K⁽¹⁰⁾ + 2.0
L⁽¹¹⁾ – 0.2 L⁽¹¹⁾ + 2.0
G⁽⁷⁾
I⁽⁸⁾ – 0.2 I⁽⁸⁾ + 2.0
D⁽⁴⁾
E⁽⁵⁾ – 0.2 E⁽⁵⁾ + 2.0
OPP50
MIN
MAX
2
2
N⁽¹²⁾
N⁽¹²⁾
B⁽²⁾ – 5
B⁽²⁾ – 5
A⁽¹⁾
A⁽¹⁾
B⁽²⁾ + 5
B⁽²⁾ + 5
C⁽³⁾ – 5
C⁽³⁾ + 5
J⁽⁹⁾ – 5
J⁽⁹⁾ – 5
J⁽⁹⁾ + 5
J⁽⁹⁾ + 5
K⁽¹⁰⁾ – 5 K⁽¹⁰⁾ + 5
L ⁽¹¹⁾ – 5
G⁽⁷⁾
L⁽¹¹⁾ + 5
I⁽⁸⁾ – 5
I⁽⁸⁾ + 5
D⁽⁴⁾
E⁽⁵⁾ – 5
E⁽⁵⁾ + 5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Copyright © 2011–2016, Texas Instruments Incorporated
Peripheral Information and Timings 137
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351