AM3359_017 Datasheet, PDF (121/253 Pages) Texas Instruments – Sitara Processors

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
(see Figure 7-7)
NO.
1
t_{c(TX_CLK)}
2
t_{w(TX_CLKH)}
3
t_{w(TX_CLKL)}
4
t_{t(TX_CLK)}
Table 7-10. Timing Requirements for GMII[x]_TXCLK - MII Mode
Cycle time, TX_CLK
Pulse duration, TX_CLK high
Pulse duration, TX_CLK low
Transition time, TX_CLK
MIN
399.96
140
140
10 Mbps
TYP
1
2
MAX
400.04
260
260
5
100 Mbps
MIN
TYP
39.996
14
14
3
MAX
40.004
26
26
5
UNIT
ns
ns
ns
ns
4
GMII[x]_TXCLK
4
Figure 7-7. GMII[x]_TXCLK Timing - MII Mode
Table 7-11. Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
(see Figure 7-8)
NO
.
10 Mbps
MIN TYP
MAX
100 Mbps
UNIT
MIN TYP MAX
t_{su(RXD-RX_CLK)}
Setup time, RXD[3:0] valid before RX_CLK
1 t_{su(RX_DV-RX_CLK)} Setup time, RX_DV valid before RX_CLK
8
t_{su(RX_ER-RX_CLK)} Setup time, RX_ER valid before RX_CLK
t_{h(RX_CLK-RXD)}
Hold time RXD[3:0] valid after RX_CLK
2 t_{h(RX_CLK-RX_DV)}
Hold time RX_DV valid after RX_CLK
8
t_{h(RX_CLK-RX_ER)}
Hold time RX_ER valid after RX_CLK
8
ns
8
ns
1
2
GMII[x]_MRCLK (Input)
GMII[x]_RXD[3:0], GMII[x]_RXDV,
GMII[x]_RXER (Inputs)
Figure 7-8. GMII[x]_RXD[3:0], GMII[x]_RXDV, GMII[x]_RXER Timing - MII Mode
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Peripheral Information and Timings 121
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