AM3359_017 Datasheet, PDF (155/253 Pages) Texas Instruments – Sitara Processors

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
SPRS717J – OCTOBER 2011 – REVISED APRIL 2016
7.7.2.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper LPDDR interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, AM335x device LPDDR
power, and AM335x device LPDDR ground connections. Table 7-37 contains the specification for the HS
bypass capacitors as well as for the power connections on the PCB.
Table 7-37. High-Speed Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
MIN
MAX UNIT
0402 10 mils
2 Distance from HS bypass capacitor to device being bypassed
3 Number of connection vias for each HS bypass capacitor⁽²⁾
250 mils
2
Vias
4 Trace length from bypass capacitor contact to connection via
30 mils
5 Number of connection vias for each AM335x VDDS_DDR and VSS terminal
1
Vias
6 Trace length from AM335x VDDS_DDR and VSS terminal to connection via
35 mils
7 Number of connection vias for each LPDDR device power and ground terminal
1
Vias
8 Trace length from LPDDR device power and ground terminal to connection via
9 AM335x VDDS_DDR HS bypass capacitor count⁽³⁾
35 mils
10
Devices
10 AM335x VDDS_DDR HS bypass capacitor total capacitance
11 LPDDR device HS bypass capacitor count⁽³⁾⁽⁴⁾
12 LPDDR device HS bypass capacitor total capacitance⁽⁴⁾
0.6
μF
8
Devices
0.4
μF
(1) LxW, 10-mil units; for example, a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Per LPDDR device.
7.7.2.1.2.8 Net Classes
Table 7-38 lists the clock net classes for the LPDDR interface. Table 7-39 lists the signal net classes, and
associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the
termination and routing rules that follow.
SIGNAL NET CLASS
ADDR_CTRL
DQ0
DQ1
Table 7-38. Clock Net Class Definitions
CLOCK NET CLASS
CK
DQS0
DQS1
AM335x PIN NAMES
DDR_CK and DDR_CKn
DDR_DQS0
DDR_DQS1
Table 7-39. Signal Net Class Definitions
ASSOCIATED CLOCK
NET CLASS
CK
DQS0
DQS1
AM335x PIN NAMES
DDR_BA[1:0], DDR_A[15:0], DDR_CSn0, DDR_CASn, DDR_RASn,
DDR_WEn, DDR_CKE
DDR_D[7:0], DDR_DQM0
DDR_D[15:8], DDR_DQM1
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Peripheral Information and Timings 155
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