AMC1304L05-Q1 Datasheet, PDF (22/39 Pages) Texas Instruments – High-Precision, Reinforced Isolated Delta-Sigma Modulators with LDO

AMC1304L05-Q1, AMC1304L25-Q1, AMC1304M05-Q1, AMC1304M25-Q1
SBAS799 – FEBRUARY 2017
www.ti.com
Feature Description (continued)
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range AGND – 6 V to 3.7 V, the input current must be limited to 10 mA because the device input electrostatic
discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are ensured only
when the differential analog input voltage remains within the specified linear full-scale range (FSR), that is
±250 mV (for the AMC1304x25-Q1) or ±50 mV (for the AMC1304x05-Q1), and within the specified input
common-mode range.
8.3.2 Modulator
The modulator implemented in the AMC1304-Q1 is a second-order, switched-capacitor, feed-forward ΔΣ
modulator, such as the one conceptualized in Figure 48. The analog input voltage V_IN and the output V₅ of the 1-
bit digital-to-analog converter (DAC) are differentiated, providing an analog voltage V₁ at the input of the first
integrator stage. The output of the first integrator feeds the input of the second integrator stage, resulting in
output voltage V₃ that is differentiated with the input signal V_IN and the output of the first integrator V₂. Depending
on the polarity of the resulting voltage V₄, the output of the comparator is changed. In this case, the 1-bit DAC
responds on the next clock pulse by changing its analog output voltage V₅, causing the integrators to progress in
the opposite direction and forcing the value of the integrator output to track the average value of the input.
f_CLKIN
V₁
V₂
V₃
V₄
V_IN
Integrator 1
Integrator 2
CMP
0V
V₅
DAC
Figure 48. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies, as shown in Figure 49. Therefore, use a low-
pass digital filter at the output of the device to increase the overall performance. This filter is also used to convert
from the 1-bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter
structure termed a sigma-delta filter module (SDFM) optimized for usage with the AMC1304-Q1 family.
Alternatively, a field-programmable gate array (FPGA) can be used to implement the digital filter.
0
-20
-40
-60
-80
-100
-120
-140
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Figure 49. Quantization Noise Shaping
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