LM4F111C4QR Datasheet, PDF (217/1113 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F111C4QR Microcontroller
auto-clock gating is disabled. The system clock source is specified in the DSLPCLKCFG register.
When the DSLPCLKCFG register is used, the internal oscillator source is powered up, if necessary,
and other clocks are powered down. If the PLL is running at the time of the WFI instruction, hardware
powers the PLL down and overrides the SYSDIV field of the active RCC/RCC2 register, to be
determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively.
When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and
frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped
during the Deep-Sleep duration. If the PIOSC is used as the PLL reference clock source, it may
continue to provide the clock during Deep-Sleep. See page 247.
Important: Before executing the WFI instruction, software must confirm that the EEPROM is not
busy by checking to see that the WORKING bit in the EEPROM Done Status (EEDONE)
register is clear.
To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the
processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the
communications modules have a Clock Control register at offset 0xFC8 in the module register space.
The CS field in the Clock Control register allows the user to select the PIOSC as the clock source
for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSC becomes
the source for the module clock as well, which allows the transmit and receive FIFOs to continue
operation while the part is in Deep-Sleep. Figure 5-6 on page 217 shows how the clocks are selected.
Figure 5-6. Module Clock Selection
Clock Control Register
PIOSC
1
0
Baud Clock
Deep Sleep
System Clock
1
Module Clock
0
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
April 25, 2012
217
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