AM1810_16 Datasheet, PDF (210/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

AM1810
SPRS709D – NOVEMBER 2010 – REVISED MARCH 2014
www.ti.com
6.25 Host-Port Interface (UHPI)
6.25.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16).
The host port interface (UHPI) provides a parallel port interface through which an external host processor
can directly access the processor's resources (configuration and program/data memories). The external
host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The UHPI
enables a host device and the processor to exchange information via internal or external memory.
Dedicated address (HPIA) and data (HPID) registers within the UHPI provide the data path between the
external host interface and the processor resources. A UHPI control register (HPIC) is available to the
host and the CPU for various configuration and interrupt functions.
6.25.2 HPI Peripheral Register Description(s)
Table 6-111. HPI Control Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
COMMENTS
0x01E1 0000
PID
Peripheral Identification Register
0x01E1 0004
PWREMU_MGMT
HPI power and emulation management register
The CPU has read/write access
to the PWREMU_MGMT register.
0x01E1 0008
-
Reserved
0x01E1 000C
GPIO_EN
General Purpose IO Enable Register
0x01E1 0010
GPIO_DIR1
General Purpose IO Direction Register 1
0x01E1 0014
GPIO_DAT1
General Purpose IO Data Register 1
0x01E1 0018
GPIO_DIR2
General Purpose IO Direction Register 2
0x01E1 001C
GPIO_DAT2
General Purpose IO Data Register 2
0x01E1 0020
GPIO_DIR3
General Purpose IO Direction Register 3
0x01E1 0024
GPIO_DAT3
General Purpose IO Data Register 3
01E1 0028
-
Reserved
01E1 002C
-
Reserved
01E1 0030
HPIC
HPI control register
The Host and the CPU both have
read/write access to the HPIC
register.
01E1 0034
01E1 0038
HPIA
(HPIAW) ⁽¹⁾
HPIA
(HPIAR) ⁽¹⁾
HPI address register
(Write)
HPI address register
(Read)
The Host has read/write access
to the HPIA registers. The CPU
has only read access to the
HPIA registers.
01E1 000C - 01E1 07FF
-
Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
210 Peripheral Information and Electrical Specifications
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM1810