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AM1810_16 Datasheet, PDF (1/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS | |||
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AM1810
SPRS709D â NOVEMBER 2010 â REVISED MARCH 2014
AM1810 ARM® Microprocessor For PROFIBUS
1 AM1810 ARM Microprocessor For PROFIBUS
1.1 Features
1
⢠375-MHz ARM926EJ-S⢠RISC MPU
⢠ARM926EJ-S Core
â 32-Bit and 16-Bit ( Thumb®) Instructions
â Single-Cycle MAC
â ARM Jazelle® Technology
â Embedded ICE-RT⢠for Real-Time Debug
⢠ARM9⢠Memory Architecture
â 16KB of Instruction Cache
â 16KB of Data Cache
â 8KB of RAM (Vector Table)
â 64KB of ROM
⢠Enhanced Direct Memory Access Controller 3
(EDMA3):
â 2 Channel Controllers
â 3 Transfer Controllers
â 64 Independent DMA Channels
â 16 Quick DMA Channels
â Programmable Transfer Burst Size
⢠128KB of On-Chip Memory
⢠1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
DDR2 Interfaces)
⢠Two External Memory Interfaces:
â EMIFA
⢠NOR (8- or 16-Bit-Wide Data)
⢠NAND (8- or 16-Bit-Wide Data)
⢠16-Bit SDRAM with 128-MB Address Space
â DDR2/Mobile DDR Memory Controller with one
of the following:
⢠16-Bit DDR2 SDRAM with 256-MB Address
Space
⢠16-Bit mDDR SDRAM with 256-MB Address
Space
⢠Three Configurable 16550-Type UART Modules:
â With Modem Control Signals
â 16-Byte FIFO
â 16x or 13x Oversampling Option
⢠LCD Controller
⢠Two Serial Peripheral Interfaces (SPIs) Each with
Multiple Chip Selects
⢠Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interfaces with Secure Data I/O (SDIO)
Interfaces
⢠Two Master and Slave Inter-Integrated Circuits
( I2C Busâ¢)
⢠One Host-Port Interface (HPI) with 16-Bit-Wide
Muxed Address and Data Bus For High Bandwidth
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⢠Programmable Real-Time Unit Subsystem
(PRUSS) with PROFIBUS
â Two Independent Programmable Real-Time Unit
(PRU) Cores
⢠32-Bit Load-Store RISC Architecture
⢠4KB of Instruction RAM per Core
⢠512 Bytes of Data RAM per Core
⢠PRUSS can be Disabled via Software to
Save Power
⢠Register 30 of Each PRU is Exported from
the Subsystem in Addition to the Normal R31
Output of the PRU Cores.
â Standard Power-Management Mechanism
⢠Clock Gating
⢠Entire Subsystem Under a Single PSC Clock
Gating Domain
â Dedicated Interrupt Controller
â Dedicated Switched Central Resource
⢠USB 1.1 OHCI (Host) with Integrated PHY (USB1)
⢠USB 2.0 OTG Port with Integrated PHY (USB0)
â USB 2.0 High- and Full-Speed Client
â USB 2.0 High-, Full-, and Low-Speed Host
â End Point 0 (Control)
â End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) RX and TX
⢠One Multichannel Audio Serial Port (McASP):
â Transmit and Receive Clocks
â Two Clock Zones and 16 Serial Data Pins
â Supports TDM, I2S, and Similar Formats
â DIT-Capable
â FIFO Buffers for Transmit and Receive
⢠Two Multichannel Buffered Serial Ports (McBSPs):
â Transmit and Receive Clocks
â Supports TDM, I2S, and Similar Formats
â AC97 Audio Codec Interface
â Telecom Interfaces (ST-Bus, H100)
â 128-Channel TDM
â FIFO Buffers for Transmit and Receive
⢠10/100 Mbps Ethernet MAC (EMAC):
â IEEE 802.3 Compliant
â MII Media-Independent Interface
â RMII Reduced Media-Independent Interface
â Management Data I/O (MDIO) Module
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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