AM1810_16 Datasheet, PDF(134/262 Page) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

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AM1810_16 Datasheet, PDF (134/262 Pages) Texas Instruments – AM1810 ARM® Microprocessor For PROFIBUS

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AM1810

SPRS709D â NOVEMBER 2010 â REVISED MARCH 2014

www.ti.com

6.15.1 McASP Peripheral Registers Description(s)

Registers for the McASP are summarized in Table 6-49. The registers are accessed through the

peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can

also be accessed through the DMA port, as listed in Table 6-50

Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-51. Note that the AFIFO Write

FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control

registers are accessed through the peripheral configuration port.

Table 6-49. McASP Registers Accessed Through Peripheral Configuration Port

BYTE ADDRESS

0x01D0 0000

0x01D0 0010

0x01D0 0014

0x01D0 0018

0x01D0 001C

0x01D0 001C

0x01D0 0020

0x01D0 0044

0x01D0 0048

0x01D0 004C

0x01D0 0050

0x01D0 0060

0x01D0 0064

0x01D0 0068

0x01D0 006C

0x01D0 0070

0x01D0 0074

0x01D0 0078

0x01D0 007C

0x01D0 0080

0x01D0 0084

0x01D0 0088

0x01D0 008C

0x01D0 00A0

0x01D0 00A4

0x01D0 00A8

0x01D0 00AC

0x01D0 00B0

0x01D0 00B4

0x01D0 00B8

0x01D0 00BC

0x01D0 00C0

0x01D0 00C4

0x01D0 00C8

0x01D0 00CC

0x01D0 0100

0x01D0 0104

0x01D0 0108

ACRONYM

REV

PFUNC

PDIR

PDOUT

PDIN

PDSET

PDCLR

GBLCTL

AMUTE

DLBCTL

DITCTL

RGBLCTL

RMASK

RFMT

AFSRCTL

ACLKRCTL

AHCLKRCTL

RTDM

RINTCTL

RSTAT

RSLOT

RCLKCHK

REVTCTL

XGBLCTL

XMASK

XFMT

AFSXCTL

ACLKXCTL

AHCLKXCTL

XTDM

XINTCTL

XSTAT

XSLOT

XCLKCHK

XEVTCTL

DITCSRA0

DITCSRA1

DITCSRA2

REGISTER DESCRIPTION

Revision identification register

Pin function register

Pin direction register

Pin data output register

Read returns: Pin data input register

Writes affect: Pin data set register (alternate write address: PDOUT)

Pin data clear register (alternate write address: PDOUT)

Global control register

Audio mute control register

Digital loopback control register

DIT mode control register

Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows

receiver to be reset independently from transmitter

Receive format unit bit mask register

Receive bit stream format register

Receive frame sync control register

Receive clock control register

Receive high-frequency clock control register

Receive TDM time slot 0-31 register

Receiver interrupt control register

Receiver status register

Current receive TDM time slot register

Receive clock check control register

Receiver DMA event control register

Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows

transmitter to be reset independently from receiver

Transmit format unit bit mask register

Transmit bit stream format register

Transmit frame sync control register

Transmit clock control register

Transmit high-frequency clock control register

Transmit TDM time slot 0-31 register

Transmitter interrupt control register

Transmitter status register

Current transmit TDM time slot register

Transmit clock check control register

Transmitter DMA event control register

Left (even TDM time slot) channel status register (DIT mode) 0

Left (even TDM time slot) channel status register (DIT mode) 1

Left (even TDM time slot) channel status register (DIT mode) 2

134 Peripheral Information and Electrical Specifications

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