LMH0384 Datasheet, PDF (20/29 Pages) National Semiconductor (TI) – 3 Gbps HD/SD SDI Extended Reach and Configurable Adaptive Cable Equalizer

LMH0384
SNLS308G – APRIL 2009 – REVISED JUNE 2015
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Typical Application (continued)
Table 2. LMH0384 Design Parameters (continued)
DESIGN PARAMETER
Output AC-coupling capacitors
Distance from Device to BNC
Input launch amplitude
REQUIREMENT
The user should check input common mode voltage. If AC coupling capacitor is
required, SDO AC-coupling capacitor is expected to be 4.7 µF ±10%.
Keep this distance as short as possible to minimize parasitic
Refer to DC Electrical Characteristics
8.2.2 Detailed Design Procedure
1. Maximum power draw for PCB regulator selection. For this use maximum power consumption in the data
sheet.
2. Closely compare schematic against typical connection diagram in the data sheet.
3. Plan out the PCB layout and component placement to minimize parasitic.
4. Consult the BNC vendor for optimum BNC landing pattern.
8.2.3 Application Curves
Figure 13 and Figure 14 depict the differential output eye diagrams for SDO, SDO at 2.97 Gbps. Measurements
were done at default operating conditions.
Time: 50 ps/div
Figure 13. 1-M B1694A PRBS10 2.97 Gbps
Time: 50 ps/div
Figure 14. 100-M B1694A PRBS10 2.97 Gbps
8.3 Dos and Don'ts
Pay special attention to the PCB layout for the high speed signals. The SMPTE specifies the requirements for
the Serial Digital Interface to transport digital video at SD, HD, and 3 Gbps data rates over coaxial cables. One of
the requirements is meeting the required Return Loss. This requirement specifies how closely the port resembles
75-Ω impedance across a specified frequency band. The SMPTE specifications also defines the use of AC-
coupling capacitors for transporting uncompressed serial data streams with heavy low frequency content. This
specification requires the use of a 1-µF AC-coupling capacitors on the input of the LMH0384 to avoid low
frequency DC wander.
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