LMH0384 Datasheet, PDF (13/29 Pages) National Semiconductor (TI) – 3 Gbps HD/SD SDI Extended Reach and Configurable Adaptive Cable Equalizer

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LMH0384
SNLS308G – APRIL 2009 – REVISED JUNE 2015
7.5 Programming
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0384 provides
register access to all of its features along with a cable length indicator, programmable output common-mode
voltage and swing, and launch amplitude optimization. There are five supported 8-bit registers in the device (see
Table 1). With SPI_EN set low, the device operates in pin mode and is footprint compatible with the LMH0344,
LMH0044, and LMH0074.
7.5.1 SPI Write
The SPI write is shown in Figure 2. The MOSI payload consists of a “0” (write command), seven address bits,
and eight data bits. The SS signal is driven low, and the 16 bits are sent to the LMH0384's MOSI input. Data is
latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI
write, SS must return high.
7.5.2 SPI Read
The SPI read is shown in Figure 3. The MOSI payload consists of a “1” (read command) and seven address bits.
The SS signal is driven low, and the eight bits are sent to the LMH0384's MOSI input. The addressed location is
accessed immediately after the rising edge of the 8^th clock and the eight data bits are shifted out on MISO
starting with the falling edge of the 8^th clock. MOSI must be tri-stated immediately after the rising edge of the 8^th
clock. After the SPI read, SS must return high.
7.5.3 Output Driver Adjustments
The output driver swing (amplitude) and offset voltage (common-mode voltage) are adjustable through SPI
register 01h.
The output swing is adjustable through bits [7:5] of SPI register 01h. The default value for these register bits is
“011” for a peak to peak differential output voltage of 700 mV_P-P. The output swing can be adjusted in 100 mV
increments from 400 mV_P-P to 800 mV_P-P.
The offset voltage is adjustable through bits [4:2] of SPI register 01h. The default value for these register bits is
“001” for an output offset of 1.25 V. The output common-mode voltage may be adjusted in 200-mV increments,
from 1.05 V to 1.85 V. It can also be set to “101” for the maximum offset voltage. At this maximum offset voltage
setting, the outputs are referenced to the positive supply and the offset voltage is around 2.1 V.
7.5.4 Launch Amplitude Optimization
The LMH0384 can compensate for attenuation of the input signal prior to the equalizer. This compensation is
useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and
is controlled by SPI register 02h.
Bit 7 of SPI register 02h is used for coarse control of the launch amplitude setting. At the default setting of “0”,
the LMH0384 operates normally and expects a launch amplitude of 800 mV_P-P. Bit 7 may be set to “1” to optimize
the LMH0384 for input signals with 6 dB of attenuation (400 mV_P-P).
Once the coarse control is set, the LMH0384 input compensation may be further fine tuned by bits [6:3] of SPI
register 02h. These bits may be used to tweak the input gain stage -22% to +40% around the coarse control
setting.
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